median.tan.rpt

用verilog编辑的中值滤波器！语言旁表有注释方便理解！

+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2C20F484C7       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                              ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                              ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                   ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                        ; To         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 154.20 MHz ( period = 6.485 ns )                    ; a2[4]~reg0                                                                                  ; d0[7]      ; clk        ; clk      ; None                        ; None                      ; 6.245 ns                ;
; N/A                                     ; 156.13 MHz ( period = 6.405 ns )                    ; a2[4]~reg0                                                                                  ; d0[6]      ; clk        ; clk      ; None                        ; None                      ; 6.165 ns                ;
; N/A                                     ; 157.43 MHz ( period = 6.352 ns )                    ; a2[0]~reg0                                                                                  ; d0[7]      ; clk        ; clk      ; None                        ; None                      ; 6.113 ns                ;
; N/A                                     ; 158.10 MHz ( period = 6.325 ns )                    ; a2[4]~reg0                                                                                  ; d0[5]      ; clk        ; clk      ; None                        ; None                      ; 6.085 ns                ;
; N/A                                     ; 158.58 MHz ( period = 6.306 ns )                    ; ram:r3|altsyncram:mem_rtl_2|altsyncram_hd61:auto_generated|ram_block1a4~porta_we_reg        ; b3[4]~reg0 ; clk        ; clk      ; None                        ; None                      ; 6.037 ns                ;
; N/A                                     ; 158.58 MHz ( period = 6.306 ns )                    ; ram:r3|altsyncram:mem_rtl_2|altsyncram_hd61:auto_generated|ram_block1a4~porta_address_reg0  ; b3[4]~reg0 ; clk        ; clk      ; None                        ; None                      ; 6.037 ns                ;
; N/A                                     ; 158.58 MHz ( period = 6.306 ns )                    ; ram:r3|altsyncram:mem_rtl_2|altsyncram_hd61:auto_generated|ram_block1a4~porta_address_reg1  ; b3[4]~reg0 ; clk        ; clk      ; None                        ; None                      ; 6.037 ns                ;
; N/A                                     ; 158.58 MHz ( period = 6.306 ns )                    ; ram:r3|altsyncram:mem_rtl_2|altsyncram_hd61:auto_generated|ram_block1a4~porta_address_reg2  ; b3[4]~reg0 ; clk        ; clk      ; None                        ; None                      ; 6.037 ns                ;
; N/A                                     ; 158.58 MHz ( period = 6.306 ns )                    ; ram:r3|altsyncram:mem_rtl_2|altsyncram_hd61:auto_generated|ram_block1a4~porta_address_reg3  ; b3[4]~reg0 ; clk        ; clk      ; None                        ; None                      ; 6.037 ns                ;
; N/A                                     ; 158.58 MHz ( period = 6.306 ns )                    ; ram:r3|altsyncram:mem_rtl_2|altsyncram_hd61:auto_generated|ram_block1a4~porta_address_reg4  ; b3[4]~reg0 ; clk        ; clk      ; None                        ; None                      ; 6.037 ns                ;
; N/A                                     ; 158.58 MHz ( period = 6.306 ns )                    ; ram:r3|altsyncram:mem_rtl_2|altsyncram_hd61:auto_generated|ram_block1a4~porta_address_reg5  ; b3[4]~reg0 ; clk        ; clk      ; None                        ; None                      ; 6.037 ns                ;
; N/A                                     ; 158.58 MHz ( period = 6.306 ns )                    ; ram:r3|altsyncram:mem_rtl_2|altsyncram_hd61:auto_generated|ram_block1a4~porta_address_reg6  ; b3[4]~reg0 ; clk        ; clk      ; None                        ; None                      ; 6.037 ns                ;
; N/A                                     ; 158.58 MHz ( period = 6.306 ns )                    ; ram:r3|altsyncram:mem_rtl_2|altsyncram_hd61:auto_generated|ram_block1a4~porta_address_reg7  ; b3[4]~reg0 ; clk        ; clk      ; None                        ; None                      ; 6.037 ns                ;
; N/A                                     ; 158.58 MHz ( period = 6.306 ns )                    ; ram:r3|altsyncram:mem_rtl_2|altsyncram_hd61:auto_generated|ram_block1a4~porta_address_reg8  ; b3[4]~reg0 ; clk        ; clk      ; None                        ; None                      ; 6.037 ns                ;
; N/A                                     ; 158.58 MHz ( period = 6.306 ns )                    ; ram:r3|altsyncram:mem_rtl_2|altsyncram_hd61:auto_generated|ram_block1a4~porta_address_reg9  ; b3[4]~reg0 ; clk        ; clk      ; None                        ; None                      ; 6.037 ns                ;
; N/A                                     ; 158.58 MHz ( period = 6.306 ns )                    ; ram:r3|altsyncram:mem_rtl_2|altsyncram_hd61:auto_generated|ram_block1a4~porta_address_reg10 ; b3[4]~reg0 ; clk        ; clk      ; None                        ; None                      ; 6.037 ns                ;