median.fit.rpt

用verilog编辑的中值滤波器！语言旁表有注释方便理解！

; Device                                                                ; EP2C20F484C7                   ;                                ;
; Minimum Core Junction Temperature                                     ; 0                              ;                                ;
; Maximum Core Junction Temperature                                     ; 85                             ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                    ;
+----------+-----------------+------------------+---------------------+-----------+----------------+---------------------------------------------------+------------------+-----------------------+
; Node     ; Action          ; Operation        ; Reason              ; Node Port ; Node Port Name ; Destination Node                                  ; Destination Port ; Destination Port Name ;
+----------+-----------------+------------------+---------------------+-----------+----------------+---------------------------------------------------+------------------+-----------------------+
; temp0[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; lpm_mult:Mult0|mult_2s01:auto_generated|result[0] ; DATAOUT          ;                       ;
; temp0[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; temp0[0]                                          ; DATAOUT          ;                       ;
; temp0[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; temp0[0]                                          ; DATAOUT          ;                       ;
; temp0[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; temp0[0]                                          ; DATAOUT          ;                       ;
; temp0[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; temp0[0]                                          ; DATAOUT          ;                       ;
; temp0[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; temp0[0]                                          ; DATAOUT          ;                       ;
; temp0[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; temp0[0]                                          ; DATAOUT          ;                       ;
; temp0[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; temp0[0]                                          ; DATAOUT          ;                       ;
; temp0[8] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; temp0[0]                                          ; DATAOUT          ;                       ;
; temp0[9] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; temp0[0]                                          ; DATAOUT          ;                       ;
+----------+-----------------+------------------+---------------------+-----------+----------------+---------------------------------------------------+------------------+-----------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in I:/panjian9/median.pin.


+-------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                           ;
+---------------------------------------------+---------------------------+
; Resource                                    ; Usage                     ;
+---------------------------------------------+---------------------------+
; Total logic elements                        ; 593 / 18,752 ( 3 % )      ;
;     -- Combinational with no register       ; 269                       ;
;     -- Register only                        ; 9                         ;
;     -- Combinational with a register        ; 315                       ;
;                                             ;                           ;
; Logic element usage by number of LUT inputs ;                           ;
;     -- 4 input functions                    ; 68                        ;
;     -- 3 input functions                    ; 384                       ;
;     -- <=2 input functions                  ; 132                       ;
;     -- Register only                        ; 9                         ;
;                                             ;                           ;
; Logic elements by mode                      ;                           ;
;     -- normal mode                          ; 373                       ;
;     -- arithmetic mode                      ; 211                       ;