cntr_modulus_la.v

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// baeckler - 06-16-2006
//
// Counter with modulus lookahead for high speed
// (1 cell per bit)

module cntr_modulus_la (clk,ena,rst,sload,sdata,sclear,q);

parameter WIDTH = 16;
parameter MOD_VAL = 50223;

input clk,ena,rst,sload,sclear;
input [WIDTH-1:0] sdata;

output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;

// This register will be 1 when the counter is 
// in the maximum value state.  Because of the 
// extra latency it needs to detect counting from
// one less than the maximum value, or sloading the
// max.
//
reg pre_maxed;
always @(posedge clk or posedge rst) begin
	if (rst) pre_maxed <= 1'b0;
	else if (ena) begin
		pre_maxed <= !sclear &&
					(!sload && (q == MOD_VAL-2) ||
					 sload && (sdata == MOD_VAL-1)) ;
	end
end

// Basic modulus counter.  The wrap signal is
// registered to improve fmax
//
always @(posedge clk or posedge rst) begin
	if (rst) q <= 0;
	else begin
		if (ena) begin
			if (sclear) q <= 0;
			else if (sload) q <= sdata;
			else q <= (pre_maxed ? 0 : q) + (pre_maxed ? 0 : 1'b1);
		end
	end
end

endmodule