in_range.v

本電子檔為 verilog cookbook,包含了通訊,影像,DSP等重要常用之verilog編碼,可作為工程師與初學者的參考手冊

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// baeckler - 02-24-2006


module in_range (dat,inr);

`include "log2.inc"
`include "highest_10.inc"

parameter LOWER_BOUND = 85;
parameter UPPER_BOUND = 120;
parameter WIDTH = 7;
parameter METHOD = 2;

// identify the most significant bit where UPPER is 1 and
// LOWER is 0
localparam SPLIT_POINT = highest_10 (UPPER_BOUND,LOWER_BOUND);
		
input [WIDTH-1:0] dat;
output inr;
wire inr;

genvar i,j;
generate
	if (METHOD == 0) begin
		////////////////////////////////////////
		// generic implementation
		////////////////////////////////////////
		assign inr = (dat >= LOWER_BOUND && dat < UPPER_BOUND);
	end
	else if (METHOD == 1) begin
		///////////////////////////////////////////////////
		// use of subtractors to implement the comparison
		///////////////////////////////////////////////////
		wire [WIDTH+1:0] result;
		wire [WIDTH:0] comp_a;
		assign comp_a = dat-LOWER_BOUND;
		assign result = comp_a-(UPPER_BOUND-LOWER_BOUND);
		assign inr = result[WIDTH+1];
	end
	else if (METHOD == 2) begin
		///////////////////////////////////////////////////
		// Demonstration of over / under / equal technique
		//   illustrated by Paul Q3 2003 slides
		//   No hard structure / chains.
		///////////////////////////////////////////////////
		wire ou_out;
		wire eq_out;

		initial begin
			$display ("%x",UPPER_BOUND[SPLIT_POINT-1:0]);
			$display ("%x",LOWER_BOUND[SPLIT_POINT-1:0]);
			$display ("%x",UPPER_BOUND[WIDTH-1:SPLIT_POINT]);
		end

		over_under ou (
			.over(!dat[SPLIT_POINT]),
			.dat(dat[SPLIT_POINT-1:0]),
			.out(ou_out)
		);
		defparam ou .WIDTH = SPLIT_POINT;
		defparam ou .METHOD = 0;
		defparam ou .UPPER_BOUND = UPPER_BOUND [SPLIT_POINT-1 : 0];
		defparam ou .LOWER_BOUND = LOWER_BOUND [SPLIT_POINT-1 : 0];

		equal_const eq (
			.dat(dat[WIDTH-1:SPLIT_POINT+1]),
			.out(eq_out)
		);
		defparam eq .WIDTH = WIDTH-SPLIT_POINT-1;
		defparam eq .CONST_VAL = UPPER_BOUND [WIDTH-1:SPLIT_POINT+1];
		defparam eq .METHOD = 0;

		assign inr = ou_out & eq_out;
	end	
endgenerate

endmodule