rc4_tb.v

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// baeckler - 04-17-2006
// RC4 testbench 
//   tests the generator using a fixed key (matching the CPP file)
//   and the synchronous reset capability
//
module rc4_tb ();

reg clk,rst,load_key,ena;
wire [7:0] dat;
wire dat_valid;

rc4 rs (.clk(clk),.ena(ena),.rst(rst),.dat(dat),.dat_valid(dat_valid),
			.key("gregg"),.load_key(load_key));
	defparam rs .KEY_BYTES = 5;
integer i;

reg fail = 0;

initial begin
	clk = 1'b0;
	rst = 1'b0;
	ena = 1'b1;
	load_key = 0;
	#10 rst = 1;
	#10 rst = 0;
	
	$display ("Keying...");
	@(posedge dat_valid);
	#10 
	$display ("First byte generated : %x expected ee",dat);
	if (dat != 8'hee) fail = 1'b1;
		
	for (i=2; i<101; i=i+1)
	begin
		@(posedge dat_valid);
	end
	#10
	$display ("100th byte generated : %x expected ab",dat);
	if (dat != 8'hab) fail = 1'b1;
	
	for (i=101; i<1001; i=i+1)
	begin
		@(posedge dat_valid);
	end
	#10
	$display ("1000th byte generated : %x expected 90",dat);
	if (dat != 8'h90) fail = 1'b1;
	
	for (i=1001; i<10001; i=i+1)
	begin
		@(posedge dat_valid);
	end
	#10
	$display ("10000th byte generated : %x expected 28",dat);
	if (dat != 8'h28) fail = 1'b1;
	
	/////////////////////////////////
	// test the synchronous reset
	/////////////////////////////////
	@(negedge clk);
	#10
	load_key = 1;
	ena = 1;
	@(posedge clk);
	@(negedge clk);
	load_key = 0;
	
	$display ("Started ReKeying at time %d...",$time);
	@(posedge dat_valid);
	#10 
	$display ("First byte generated : %x expected ee",dat);
	if (dat != 8'hee) fail = 1'b1;
	
	for (i=2; i<101; i=i+1)
	begin
		@(posedge dat_valid);
	end
	#10
	$display ("100th byte generated : %x expected ab",dat);
	if (dat != 8'hab) fail = 1'b1;
	
	for (i=101; i<1001; i=i+1)
	begin
		@(posedge dat_valid);
	end
	#10
	$display ("1000th byte generated : %x expected 90",dat);
	if (dat != 8'h90) fail = 1'b1;
	

	for (i=1001; i<10001; i=i+1)
	begin
		@(posedge dat_valid);
	end
	#10
	$display ("10000th byte generated : %x expected 28",dat);

	if (!fail) $display ("PASS");
	$stop();
end

// fiddle the enable randomly
always @(negedge clk) begin
	ena = $random;
end

always begin
	#100 clk = ~clk;
end

endmodule