reed_sol.cpp

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	fprintf (stdout,"//////////////////////////////\n\n");

	fprintf (stdout,"wire [%d:0] root_match;\n",n-1);
	fprintf (stdout,"wire [%d:0] elprt_0 = elp[%d:0];\n",
		symbol_size*(t+1)-1,symbol_size*(t+1)-1);

	for (i=0;i<n;i++)
	{
		fprintf (stdout,"wire [%d:0] elprt_%d;\n",symbol_size*(t+1)-1,i+1);
		fprintf (stdout,"error_loc_poly_roots elpr%d (.elp_in(elprt_%d),\n",i,i);
		fprintf (stdout,"     .elp_out(elprt_%d),.match(root_match[%d]));\n\n",i+1,i);
	}

	fprintf (stdout,"//////////////////////////////\n");
	fprintf (stdout,"// Find the correction values\n");
	fprintf (stdout,"//////////////////////////////\n\n");

	fprintf (stdout,"wire [%d:0] val_emp_0 = emp[%d:0];\n",
		symbol_size*(t+1)-1,symbol_size*(t+1)-1);
	fprintf (stdout,"wire [%d:0] error_val;\n\n",symbol_size*n-1);

	for (i=0;i<n;i++)
	{
		fprintf (stdout,"wire [%d:0] val_emp_%d;\n",symbol_size*(t+1)-1,i+1);
		fprintf (stdout,"wire [%d:0] sum_of_odds_%d =\n",symbol_size-1,i+1);
		first = true;	
		for (h=symbol_size; h<symbol_size*(t+1); h+=(2*symbol_size))
		{
			if (!first) fprintf (stdout," ^\n");
			fprintf (stdout,"     elprt_%d[%d:%d]",i+1,h+symbol_size-1,h);
			first = false;
		}
		fprintf (stdout,";\n\n");

		fprintf (stdout,"error_value_round evr%d (.emp_in(val_emp_%d),\n",i,i);
		fprintf (stdout,"     .emp_out(val_emp_%d),\n",i+1);
		fprintf (stdout,"     .deriv_term(sum_of_odds_%d),\n",i+1);
		fprintf (stdout,"     .error_pos(root_match[%d]),\n",i);
		fprintf (stdout,"     .error_val(error_val[%d:%d]));\n\n",
							symbol_size*(i+1)-1,symbol_size*i);
	}

	fprintf (stdout,"//////////////////////////////\n");
	fprintf (stdout,"// Apply correction values\n");
	fprintf (stdout,"//////////////////////////////\n\n");

	for (i=0;i<n;i++)
	{
		fprintf (stdout,"assign rx_data_corrected[%d:%d] = rx_data[%d:%d] ^ error_val[%d:%d];\n",
			symbol_size*(i+1)-1,symbol_size*i,
			symbol_size*(i+1)-1,symbol_size*i,
			symbol_size*((n-1-i)+1)-1,symbol_size*(n-1-i)
		);
	}
	
	fprintf (stdout,"endmodule\n");
}


///////////////////////////////////////////

void build_flat_decoder_tb (
	int symbol_size,
	int data_symbols
)
{
	int n = (1 << symbol_size) - 1;
	int k = data_symbols;
	int t = (n - k) / 2;

	fprintf (stdout,"\n///////////////////////////////////////////\n\n");
	
	fprintf (stdout,"module flat_decoder_tb ();\n");
	fprintf (stdout,"reg [%d:0] din;\n",symbol_size-1);
	fprintf (stdout,"reg clk,rst,first_din;\n");
	fprintf (stdout,"wire [%d:0] parity;\n",symbol_size*2*t-1);
	fprintf (stdout,"reg [%d:0] tx_buffer;\n",k*symbol_size-1);
	fprintf (stdout,"wire [%d:0] tx_data = {tx_buffer,parity};\n",n*symbol_size-1);
	fprintf (stdout,"reg [%d:0] err;\n",n*symbol_size-1);
	fprintf (stdout,"wire [%d:0] rx_data = tx_data ^ err;\n",n*symbol_size-1);

	fprintf (stdout,"wire [%d:0] rx_data_corrected;\n\n",symbol_size*n-1);
	
	fprintf (stdout,"encoder enc (.clk(clk),.ena(1'b1),.rst(rst),.shift(1'b0),.first_din(first_din),.din(din),.parity(parity));\n\n");
	fprintf (stdout,"flat_decoder fd (.rx_data(rx_data),.rx_data_corrected(rx_data_corrected));\n\n");
	
	fprintf (stdout,"initial begin\n");
	fprintf (stdout,"  clk = 0;\n");
	fprintf (stdout,"  rst = 0;\n");
	fprintf (stdout,"  first_din = 1'b1;\n");
	fprintf (stdout,"  #10 rst = 1;\n");
	fprintf (stdout,"  #10 rst = 0;\n");
	fprintf (stdout,"end\n\n");
	
	fprintf (stdout,"always begin\n");
	fprintf (stdout,"  #1000 clk = ~clk;\n");
	fprintf (stdout,"end\n\n");
	
	fprintf (stdout,"always @(negedge clk) begin\n");
	fprintf (stdout,"  din = $random;\n");
	fprintf (stdout,"end\n\n");

	fprintf (stdout,"always @(posedge clk) begin\n");
	fprintf (stdout,"  tx_buffer = (tx_buffer << %d) | din;\n",symbol_size);
	fprintf (stdout,"end\n\n");

	fprintf (stdout,"integer i;\n");
	fprintf (stdout,"initial begin\n");
	fprintf (stdout,"  #100\n");
	fprintf (stdout,"  @(negedge clk);\n");
	fprintf (stdout,"  err = 0;\n");
	fprintf (stdout,"  first_din = 1'b1;\n");
	fprintf (stdout,"  @(posedge clk);\n");
	fprintf (stdout,"  @(negedge clk);\n");
	fprintf (stdout,"  first_din = 1'b0;\n");
	fprintf (stdout,"  for (i=0; i<%d; i=i+1) begin\n",k-1);
	fprintf (stdout,"    @(posedge clk);\n");
	fprintf (stdout,"    @(negedge clk);\n");
	fprintf (stdout,"  end\n");
	fprintf (stdout,"  $display (\"tx data %%x\",tx_data);\n");
	fprintf (stdout,"  $display (\"  correct rx data %%x\",rx_data);\n");
	fprintf (stdout,"  $display (\"    rx_data_corrected %%x\",rx_data_corrected);\n");
	fprintf (stdout,"  if (rx_data_corrected !== tx_data) begin\n");
	fprintf (stdout,"    $display (\"Error : correct data was fixed incorrectly?\");\n");
	fprintf (stdout,"    $stop();\n");
	fprintf (stdout,"  end\n");
	fprintf (stdout,"  #1 err = 1'b1;\n");
	fprintf (stdout,"  for (i=0; i<%d; i=i+1) begin\n",n*symbol_size);
	fprintf (stdout,"    #1\n");
	fprintf (stdout,"    $display (\"  rx data with error%%x\",rx_data);\n");
	fprintf (stdout,"    $display (\"    rx_data_corrected %%x\",rx_data_corrected);\n");
	fprintf (stdout,"    if (rx_data_corrected !== tx_data) begin\n");
	fprintf (stdout,"      $display (\"Error : data was not corrected\");\n");
	fprintf (stdout,"      $stop();\n");
	fprintf (stdout,"    end\n");
	fprintf (stdout,"    err = err << 1;\n");
	fprintf (stdout,"  end\n");
	fprintf (stdout,"  $display (\"PASS\");\n");
	fprintf (stdout,"  $stop();\n");
	fprintf (stdout,"end\n\n");

	fprintf (stdout,"endmodule\n");

}	

///////////////////////////////////////

void build_reed_sol_tx (
	int symbol_size,
	int data_symbols
)
{
	int n = (1 << symbol_size) - 1;
	int k = data_symbols;
	int t = (n - k) / 2;

	fprintf (stdout,"\n///////////////////////////////////////////\n");
	fprintf (stdout,"// Iterative TX unit\n");
	fprintf (stdout,"///////////////////////////////////////////\n\n");
		
	fprintf (stdout,"module reed_sol_tx (\n");
	fprintf (stdout,"   clk,rst,\n");
	fprintf (stdout,"   first_din,din,din_valid,ready_for_din,\n");
	fprintf (stdout,"   dout,dout_valid\n");
	fprintf (stdout,");\n\n");

	fprintf (stdout,"input clk,rst;\n");
	fprintf (stdout,"input first_din;  // 1 for the first symbol of each word\n");
	fprintf (stdout,"input [%d:0] din; // most significant symbol first\n",
			symbol_size-1);
	fprintf (stdout,"input din_valid;		// din data is valid\n");
	fprintf (stdout,"output ready_for_din;  // din will be accepted\n");
	fprintf (stdout,"output [%d:0] dout;        // TX data out\n",symbol_size-1);
	fprintf (stdout,"output dout_valid;         // TX data is valid\n");
	fprintf (stdout,"\n");
	
	
	fprintf (stdout,"reg [%d:0] dout;\n",symbol_size-1);
	fprintf (stdout,"reg dout_valid,ready_for_din;\n\n");
	
	fprintf (stdout,"reg [%d:0] symbol_cntr;\n\n",log_2(n-1)-1);
	
	fprintf (stdout,"wire enc_ena;\n");
	fprintf (stdout,"wire [%d:0] parity;\n\n",2*t*symbol_size-1);
	
	fprintf (stdout,"assign enc_ena = !ready_for_din | din_valid;\n");
	fprintf (stdout,"encoder enc (.clk(clk),.rst(rst),.ena(enc_ena),.shift(!ready_for_din),\n");
	fprintf (stdout,"   .first_din(first_din),.din(din),.parity(parity));\n\n");
	
	fprintf (stdout,"always @(posedge clk or posedge rst) begin\n");
	fprintf (stdout,"  if (rst) begin\n");
	fprintf (stdout,"      symbol_cntr <= 0;\n");
	fprintf (stdout,"      ready_for_din <= 1'b1;\n");
	fprintf (stdout,"      dout_valid <= 1'b0;\n");
	fprintf (stdout,"  end\n");
	fprintf (stdout,"  else begin\n");
	fprintf (stdout,"      if (ready_for_din) begin\n");
	fprintf (stdout,"          if (din_valid) begin\n");
	fprintf (stdout,"              // Pass the data symbols along\n");
	fprintf (stdout,"              dout <= din;\n");
	fprintf (stdout,"              dout_valid <= 1'b1;\n");
	fprintf (stdout,"              symbol_cntr <= symbol_cntr + 1'b1;\n");
	fprintf (stdout,"              if (symbol_cntr == %d) begin\n",k-1);
	fprintf (stdout,"                 // data is complete, start sending parity next\n");
	fprintf (stdout,"                 ready_for_din <= 1'b0;\n");
	fprintf (stdout,"              end\n");
	fprintf (stdout,"          end\n");
	fprintf (stdout,"          else begin\n");
	fprintf (stdout,"              // I want more data, it's not available yet\n");
	fprintf (stdout,"              dout_valid <= 1'b0;\n");
	fprintf (stdout,"          end\n");
	fprintf (stdout,"      end\n");
	fprintf (stdout,"      else begin\n");
	fprintf (stdout,"          // Send the parity symbols\n");
	fprintf (stdout,"          symbol_cntr <= symbol_cntr + 1'b1;\n");
	fprintf (stdout,"          dout <= parity[%d:%d];\n",
									2*t*symbol_size-1,2*t*symbol_size-symbol_size);
	fprintf (stdout,"          dout_valid <= 1'b1;\n");
	fprintf (stdout,"          if (symbol_cntr == %d) begin\n",n-1);
	fprintf (stdout,"              // parity almost complete, request more data\n");
	fprintf (stdout,"              ready_for_din <= 1'b1;\n");
	fprintf (stdout,"              symbol_cntr <= 0;\n");
	fprintf (stdout,"          end\n");
	fprintf (stdout,"      end\n");	
	fprintf (stdout,"  end\n");
	fprintf (stdout,"end\n");	

	fprintf (stdout,"endmodule\n");	

}

///////////////////////////////////////

void build_reed_sol_rx (
	int symbol_size,
	int data_symbols
)
{
	int n = (1 << symbol_size) - 1;
	int k = data_symbols;
	int t = (n - k) / 2;
	
	int h = 0;
	bool first = true;

	fprintf (stdout,"\n///////////////////////////////////////////\n");
	fprintf (stdout,"// Iterative RX unit\n");
	fprintf (stdout,"///////////////////////////////////////////\n\n");
	
	fprintf (stdout,"module reed_sol_rx (\n");
	fprintf (stdout,"   clk,rst,\n");
	fprintf (stdout,"   first_din,din,din_valid,ready_for_din,\n");
	fprintf (stdout,"   dout,dout_valid,corrected_bits,failure\n");
	fprintf (stdout,");\n\n");

	fprintf (stdout,"input clk,rst;\n");
	fprintf (stdout,"input first_din;  // 1 for the first symbol of each word\n");
	fprintf (stdout,"input [%d:0] din; // most significant symbol first\n",
			symbol_size-1);
	fprintf (stdout,"input din_valid;		  // din data is valid\n");
	fprintf (stdout,"output ready_for_din;    // din will be accepted\n");
	fprintf (stdout,"output [%d:0] dout;        // Corrected data out\n",symbol_size-1);
	fprintf (stdout,"output dout_valid;         // data out available\n");
	fprintf (stdout,"output [%d:0] corrected_bits;   // bits changed to fix dout\n",symbol_size-1);
	fprintf (stdout,"output failure;            // too many errors to correct this symbol\n");
	
	fprintf (stdout,"\n");
	
	
	fprintf (stdout,"reg [%d:0] dout;\n",symbol_size-1);
	fprintf (stdout,"reg [%d:0] corrected_bits;\n",symbol_size-1);
	fprintf (stdout,"reg dout_valid,ready_for_din,failure;\n\n");
	
	fprintf (stdout,"reg [%d:0] symbol_cntr;\n\n",log_2(n-1)-1);
	
	fprintf (stdout,"/////////////////////////////////\n");
	fprintf (stdout,"// syndrome computation\n");
	fprintf (stdout,"/////////////////////////////////\n");
	fprintf (stdout,"reg [%d:0] syndrome;\n",2*t*symbol_size-1);
	fprintf (stdout,"wire [%d:0] next_syndrome;\n",2*t*symbol_size-1);
	fprintf (stdout,"reg syndrome_ready,leading_syndrome_ready;\n\n");

	fprintf (stdout,"wire syndrome_ena = ready_for_din & din_valid;\n");
	fprintf (stdout,"syndrome_round sr (.rx_data (din),\n");
	fprintf (stdout,"       .syndrome_in(first_din ? %d'b0 : syndrome),\n",2*t*symbol_size);
	fprintf (stdout,"       .syndrome_out(next_syndrome),\n");
	fprintf (stdout,"       .skip_mult(leading_syndrome_ready)\n");
	fprintf (stdout,");\n\n");
	
	fprintf (stdout,"always @(posedge clk or posedge rst) begin\n");
	fprintf (stdout,"  if (rst) begin\n");
	fprintf (stdout,"    syndrome <= %d'b0;\n",2*t*symbol_size);
	fprintf (stdout,"    syndrome_ready <= 1'b0;\n");
	fprintf (stdout,"    leading_syndrome_ready <= 1'b0;\n");
	fprintf (stdout,"    symbol_cntr <= 0;\n");
	fprintf (stdout,"    ready_for_din <= 1'b1;\n");
	fprintf (stdout,"  end\n");
	fprintf (stdout,"  else begin\n");
	fprintf (stdout,"    if (syndrome_ena) begin\n");
	fprintf (stdout,"        syndrome <= next_syndrome;\n");
	fprintf (stdout,"        if (symbol_cntr == %d) begin\n",n-1);
	fprintf (stdout,"            // syndrome is complete\n");
	fprintf (stdout,"            // accept more immediately, and signal syn ready\n");
	fprintf (stdout,"            ready_for_din <= 1'b1;\n");
	fprintf (stdout,"            syndrome_ready <= 1'b1;\n");
	fprintf (stdout,"            leading_syndrome_ready <= 1'b0;\n");
	fprintf (stdout,"            symbol_cntr <= 0;\n");
	fprintf (stdout,"        end\n");
	fprintf (stdout,"        else begin\n");
	fprintf (stdout,"            if (symbol_cntr == %d) begin\n",n-2);
	fprintf (stdout,"               leading_syndrome_ready <= 1'b1;\n");
	fprintf (stdout,"            end\n");
	fprintf (stdout,"            symbol_cntr <= symbol_cntr + 1'b1;\n");
	fprintf (stdout,"            syndrome_ready <= 1'b0;\n");
	fprintf (stdout,"        end\n");
	fprintf (stdout,"    end\n");
	fprintf (stdout,"  end\n");
	fprintf (stdout,"end\n\n");
	
	
	fprintf (stdout,"////////////////////////////////////////\n");
	fprintf (stdout,"// Error location poly computation\n");
	fprintf (stdout,"////////////////////////////////////////\n\n");

	fprintf (stdout,"reg [%d:0] step;\n",log_2(2*t)-1);
	fprintf (stdout,"reg [%d:0] order;\n",log_2(2*t-1)-1);
	fprintf (stdout,"wire [%d:0] next_order;\n",log_2(2*t-1)-1);
	fprintf (stdout,"reg [%d:0] elp;\n",symbol_size*2*t-1);
	fprintf (stdout,"wire [%d:0] next_elp;\n",symbol_size*2*t-1);
	fprintf (stdout,"reg [%d:0] step_syndrome;\n",symbol_size*2*t-1);
	fprintf (stdout,"reg [%d:0] saved_syndrome;\n",symbol_size*2*t-1);
	fprintf (stdout,"reg [%d:0] correction;\n",symbol_size*2*t-1);
	fprintf (stdout,"wire [%d:0] next_correction;\n\n",symbol_size*2*t-1);
	fprintf (stdout,"wire elp_ena = 1'b1;\n");
	fprintf (stdout,"reg last_syndrome_ready;\n");
	fprintf (stdout,"reg elp_ready;\n");
	fprintf (stdout,"reg first_elp;\n");
	fprintf (stdout,"wire final_elp = (step == %d) ? 1'b1 : 1'b0;\n",2*t);

	fprintf (stdout,"wire elpr_wait;\n\n");
	fprintf (stdout,"always @(posedge clk or posedge rst) begin\n");
	fprintf (stdout,"  if (rst) first_elp <= 1'b0;\n");
	fprintf (stdout,"  else begin\n");
	fprintf (stdout,"    if (leading_syndrome_ready) first_elp <= 1'b1;\n");
	fprintf (stdout,"    else if (!elpr_wait) first_elp <= 1'b0;\n");
	fprintf (stdout,"  end\n");
	fprintf (stdout,"end\n\n");

	fprintf (stdout,"error_loc_poly_round_multi_step elpr (\n");
	fprintf (stdout,"    .step(step),\n",log_2(2*t));
	fprintf (stdout,"    .order_in(order),\n",log_2(2*t-1));
	fprintf (stdout,"    .order_out(next_order),\n");
	fprintf (stdout,"    .elp_in(elp),\n",symbol_size*2*t);
	fprintf (stdout,"    .elp_out(next_elp),\n");
	fprintf (stdout,"    .step_syndrome(step_syndrome),\n");
	fprintf (stdout,"    .correction_in(correction),\n");
	fprintf (stdout,"    .clk(clk),.rst(rst),.sync(leading_syndrome_ready),\n");
	fprintf (stdout,"    .elpr_wait(elpr_wait),\n");
	fprintf (stdout,"    .correction_out(next_correction));\n");
	
	fprintf (stdout,"always @(posedge clk or posedge rst) begin\n");
	fprintf (stdout,"  if (rst) begin\n");
	fprintf (stdout,"      step <= 0;\n");
	fprintf (stdout,"      order <= 0;\n");
	fprintf (stdout,"      correction <= 0;\n");
	fprintf (stdout,"      step_syndrome <= 0;\n");
	fprintf (stdout,"      elp_ready <= 1'b0;\n");
	fprintf (stdout,"  end\n");
	fprintf (stdout,"  else if (elp_ena) begin\n");
	fprintf (stdout,"      if (leading_syndrome_ready) begin\n");
	fprintf (stdout,"         step <= 1;\n");
	fprintf (stdout,"         order <= 0;\n");
	fprintf (stdout,"         correction <= {%d'b1,%d'b0};\n",
								symbol_size*2*t-symbol_size,symbol_size);
	fprintf (stdout,"         elp <= %d'b1;\n",symbol_size*2*t);
	fprintf (stdout,"         step_syndrome <= {%d'b0,next_syndrome[%d:0]};\n",
								symbol_size*(2*t-1),symbol_size-1);
	fpr