cnt10.vhd

VHDL编写的数字显示型频率测试仪

library ieee;
use ieee.std_logic_1164.all;

entity cnt10 is
  port( clk: in std_logic;
        clr: in std_logic;
        ena : in std_logic;
        cq: out integer range 0 to 15;
        carry_out: out std_logic);
  end cnt10;

architecture behav of cnt10 is
   SIGNAL CQI : INTEGER RANGE 0 TO 15 ;
BEGIN
   process(clk,clr,ena) 
     begin 
       if clr= '1'  then  cqi<=0;
       elsif  clk'event and clk= '1' then
          if ena ='1'  then
             if cqi<9 then cqi<=cqi+1;
             else cqi<=0;  end if;
          end if;
      end if;
   end process;
process(cqi)
  begin
     if cqi=9 then carry_out<='1';
              else carry_out<='0';
     END IF;
end process;
cq<=cqi;
end ;