testctl.vhd

VHDL编写的数字显示型频率测试仪

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TESTCTL IS
 PORT ( CLK : IN STD_LOGIC ;
        TSTEN : OUT STD_LOGIC;
        CLR_CNT : OUT STD_LOGIC;
        Load : OUT STD_LOGIC) ;
END TESTCTL ;
ARCHITECTURE behav OF TESTCTL IS
    SIGNAL Div2CLK : STD_LOGIC;
BEGIN
    PROCESS(CLK)
    BEGIN
        IF CLK'EVENT AND CLK='1' THEN
           Div2CLK<=NOT Div2CLK ;
        END IF;
    END PROCESS;
    PROCESS(CLK,Div2CLK)
    BEGIN
    IF CLK='0' AND Div2CLK='0' THEN CLR_CNT<='1';
    ELSE CLR_CNT<='0';
    END IF;
    END PROCESS;
    Load<= NOT Div2CLK;
    TSTEN<= Div2CLK;
END behav;