1013.tan.qmsg

用verilog写的对ad0809的控制

{ "Info" "ITDB_FULL_TCO_RESULT" "clk led8 led8~reg0 9.770 ns register " "Info: tco from clock \"clk\" to destination pin \"led8\" through register \"led8~reg0\" is 9.770 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.874 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad0809.v" "" { Text "F:/72quartus/ADcontrol/ad0809.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 479 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 479; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ad0809.v" "" { Text "F:/72quartus/ADcontrol/ad0809.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.666 ns) 2.874 ns led8~reg0 3 REG LCFF_X14_Y5_N9 4 " "Info: 3: + IC(0.929 ns) + CELL(0.666 ns) = 2.874 ns; Loc. = LCFF_X14_Y5_N9; Fanout = 4; REG Node = 'led8~reg0'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.595 ns" { clk~clkctrl led8~reg0 } "NODE_NAME" } } { "ad0809.v" "" { Text "F:/72quartus/ADcontrol/ad0809.v" 62 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.84 % ) " "Info: Total cell delay = 1.806 ns ( 62.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.068 ns ( 37.16 % ) " "Info: Total interconnect delay = 1.068 ns ( 37.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.874 ns" { clk clk~clkctrl led8~reg0 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "2.874 ns" { clk {} clk~combout {} clk~clkctrl {} led8~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "ad0809.v" "" { Text "F:/72quartus/ADcontrol/ad0809.v" 62 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.592 ns + Longest register pin " "Info: + Longest register to pin delay is 6.592 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led8~reg0 1 REG LCFF_X14_Y5_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y5_N9; Fanout = 4; REG Node = 'led8~reg0'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led8~reg0 } "NODE_NAME" } } { "ad0809.v" "" { Text "F:/72quartus/ADcontrol/ad0809.v" 62 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.326 ns) + CELL(3.266 ns) 6.592 ns led8 2 PIN PIN_88 0 " "Info: 2: + IC(3.326 ns) + CELL(3.266 ns) = 6.592 ns; Loc. = PIN_88; Fanout = 0; PIN Node = 'led8'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "6.592 ns" { led8~reg0 led8 } "NODE_NAME" } } { "ad0809.v" "" { Text "F:/72quartus/ADcontrol/ad0809.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.266 ns ( 49.54 % ) " "Info: Total cell delay = 3.266 ns ( 49.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.326 ns ( 50.46 % ) " "Info: Total interconnect delay = 3.326 ns ( 50.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "6.592 ns" { led8~reg0 led8 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "6.592 ns" { led8~reg0 {} led8 {} } { 0.000ns 3.326ns } { 0.000ns 3.266ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.874 ns" { clk clk~clkctrl led8~reg0 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "2.874 ns" { clk {} clk~combout {} clk~clkctrl {} led8~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "6.592 ns" { led8~reg0 led8 } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "6.592 ns" { led8~reg0 {} led8 {} } { 0.000ns 3.326ns } { 0.000ns 3.266ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "d2 altera_auto_signaltap_0_d2_ae 9.718 ns Longest " "Info: Longest tpd from source pin \"d2\" to destination pin \"altera_auto_signaltap_0_d2_ae\" is 9.718 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns d2 1 PIN PIN_40 4 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_40; Fanout = 4; PIN Node = 'd2'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { d2 } "NODE_NAME" } } { "ad0809.v" "" { Text "F:/72quartus/ADcontrol/ad0809.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.239 ns) + CELL(0.319 ns) 7.543 ns altera_auto_signaltap_0_d2_signaltap_lcell 2 COMB LCCOMB_X12_Y7_N0 1 " "Info: 2: + IC(6.239 ns) + CELL(0.319 ns) = 7.543 ns; Loc. = LCCOMB_X12_Y7_N0; Fanout = 1; COMB Node = 'altera_auto_signaltap_0_d2_signaltap_lcell'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "6.558 ns" { d2 altera_auto_signaltap_0_d2_signaltap_lcell } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.175 ns) + CELL(0.000 ns) 9.718 ns altera_auto_signaltap_0_d2_ae 3 PIN LCCOMB_X21_Y12_N0 0 " "Info: 3: + IC(2.175 ns) + CELL(0.000 ns) = 9.718 ns; Loc. = LCCOMB_X21_Y12_N0; Fanout = 0; PIN Node = 'altera_auto_signaltap_0_d2_ae'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.175 ns" { altera_auto_signaltap_0_d2_signaltap_lcell altera_auto_signaltap_0_d2_ae } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.304 ns ( 13.42 % ) " "Info: Total cell delay = 1.304 ns ( 13.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.414 ns ( 86.58 % ) " "Info: Total interconnect delay = 8.414 ns ( 86.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "9.718 ns" { d2 altera_auto_signaltap_0_d2_signaltap_lcell altera_auto_signaltap_0_d2_ae } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "9.718 ns" { d2 {} d2~combout {} altera_auto_signaltap_0_d2_signaltap_lcell {} altera_auto_signaltap_0_d2_ae {} } { 0.000ns 0.000ns 6.239ns 2.175ns } { 0.000ns 0.985ns 0.319ns 0.000ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2