basic_base2_mul.v

来自「精通verilog HDL语言编程源码之2--常用乘法器设计」· Verilog 代码 · 共 28 行

// 通用N比特乘M比特的二进制乘法器
module basic_base2_mul(x_in, y_in, p_out);	
	parameter 	N = 8,
				M = 4;
	input  [N-1:0] x_in;
	input  [M-1:0] y_in;
	output [N+M-1:0] p_out;
	reg	   [N+M-1:0] p_out;

	integer i;
	reg [M:0] wires[N:0];
	always @(x_in or y_in)begin
		for(i=0; i<N-1; i=i+1)begin
			wires[i+1] = mult_by_1(x_in[i], wires[i][M:1], y_in); 
			p_out[i] = wires[i+1][0];
		end
		p_out[N+M-1:N] = wires[N][M:1];
	end

	function [M:0] mult_by_1;		// 用以实现1比特乘法器
		input			xi;
		input  [M-1:0] 	A, B;
	
		if(xi)	mult_by_1 = A + B;
		else	mult_by_1 = A;
	endfunction
endmodule