uart_tran.tan.summary

UART串口的传送verilog原程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.894 ns
From           : wr_en
To             : data_reg[6]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.280 ns
From           : cnt[10]
To             : clk_equ
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.719 ns
From           : reset
To             : contral
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 221.43 MHz ( period = 4.516 ns )
From           : cnt[4]
To             : cnt[11]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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