mul4_1_if.v

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

//-------------------------------------------------------
//4-bit multiplexer with if...else if...else if...else...
//Filenale : mul4_1_if
//-------------------------------------------------------
module mul4_1_if(y, s, i);
output y;
input [1:0] s;   //Select line
input [3:0] i;    //Input data

reg y;
always @ (s or i)
  begin
    if (s==2'b00)
      y = i[0];
    else if (s==2'b01)
      y = i[1];
    else if (s==2'b10)
      y = i[2];
    else
      y = i[3];
  end

endmodule