adder8_for_tb.tf

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

module testbench();

// Inputs
    reg [7:0] a;
    reg [7:0] b;
    reg cin;


// Outputs
    wire [7:0] sum;
    wire cout;

// Instantiate the UUT
    adder8_for uut (.sum(sum), .cout(cout), .a(a), .b(b), .cin(cin));

// Initialize Inputs
 initial $monitor($time, "sum=%h, cout=%b, a=%h, b=%h, cin=%b", sum, cout, a, b, cin);

// Initialize Inputs
initial begin
  cin = 0;
  a = 8'd00;
  b = 8'd00;
end

//Set different values at different time
initial begin
  #10 begin cin=0; a=8'd25; b=8'd75; end
  #10 begin cin=1; a=8'd96; b=8'd88; end
  #10 begin cin=1; a=8'd255; b=8'd255; end
  #10 begin cin=1; a=8'd127; b=8'd127; end
end

 initial #50 $finish; //Complete simulation after 90 units


endmodule