delay_line.v

延迟线模块的verilog代码

//--------------------------------------------------------------------------
//
// File name    : delay_line.v
// Title        : delay line unit
// Library      : Rotate
// Created On   : 2007-4-17 14:06
// Developers   : MeiHB
//              : 
// Function     : delay line.
// ----------------------------------------------------------------------
// Revision History :
// ----------------------------------------------------------------------
//   Ver  	:| Author		:| Mod. Date 	:|    Changes Made:
//   v1.0  	:| MeiHB	  :| 2007-04-18	:| Firstly Generated
//   v1.1		:| MeiHB		:| 2007-04-25 :| divide one always@ into two always@                                    
//	 V1.2		:| MeiHB 		:| 2007-05-08	:| add a input signal: initial_dl
//	 V1.3		:| LiJiejun :| 2007-05-26	:| add "clr" : high active;
// ----------------------------------------------------------------------
`include "../include/config.inc"
`include "../include/timescale.v"
`define ram_length 640
//----------------------------------------------------------
//											module define
//----------------------------------------------------------
module delay_line17(
	//input ports
	clk,
	rst_n,
	stop_A,
	clr,
	initial_dl,	
	dl_length,		
	delay_din,	
	//output ports				
	delay_dout					 
	);
//----------------------------------------------------------
//											port declare
//----------------------------------------------------------
parameter DELAY = 1;
parameter width_i =  17;	//input voxel width
parameter width_o = 17;		//output voxel width
parameter width_m = 10;
parameter width_dl = 10;	  //delay line width

input  clk,rst_n,stop_A;	//control signal
input clr;		           
input initial_dl;   //restart the delay line, and ready to get delay line length
input [width_dl-1:0]dl_length;	//length of delay line 
input	[width_i-1:0]delay_din;			  //write data in delay line.

output [width_o-1:0] delay_dout;		  //read data from delay line.

//----------------------------------------------------------
//											Local Wires declare
//---------------------------------------------------------- 
reg CENR;								//delay line read enable,low level enable
reg CENW;								//delay line write enable,low level enable
reg [width_m-1:0]ADR ;		//delay line read address
reg [width_m-1:0]ADW;		//delay line write address
reg [width_o-1:0]delay_dout;

wire [width_o-1:0]delay_out;
//----------------------------------------------------------
//											module body
//											delay line control
//----------------------------------------------------------
always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			begin
			CENR <= #DELAY 1;				//read disable
			ADR <= #DELAY 0;					//initial read address
			end
		else if(clr)
			begin
			CENR <= #DELAY 1;				//read disable
			ADR <= #DELAY 0;					//initial read address
			end	
		else if(initial_dl)
			ADR	<= #DELAY 0;
		else if(!stop_A)
			begin
			CENR <= #DELAY 0;
			if(ADR >= `ram_length-1)
			   ADR <= #DELAY 0;
			else
			   ADR <= #DELAY ADR + 1;
			end
		else
			CENR <= #DELAY 1;
	end
/////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////	
	
always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			begin
			CENW <= #DELAY 1;					//write disable
			ADW <= #DELAY 0;					//initial write address, 
			end
		else if(clr)
			begin
			CENW <= #DELAY 1;					//write disable
			ADW <= #DELAY 0;					//initial write address, 
			end
		else if(initial_dl)
			ADW <= #DELAY dl_length -1;	//|ADW-ADR|=dl_length
		else if(!stop_A)
			begin
			CENW <= #DELAY 0;
			if(ADW >= `ram_length-1)
				ADW <= #DELAY 0;
		   else
		      ADW <= #DELAY ADW+1 ;
			end
		else
			CENW <= #DELAY 1;
	end

//----------------------------------------------------------
//ram module
`ifdef IM1_CFG_FPGA_MODE
RFTP640X17M4_FA RAM_delay_line(
	.clock(clk),
	.data(delay_din),
	.rdaddress(ADR),
	.rden(!stop_A),
	.wraddress(ADW),
	.wren(!stop_A),
	.q(delay_out)
	);

`else
RFTP640X17M4 RAM_delay_line(
   .DAOUT(delay_out),
   .ADA(ADR),
   .ADB(ADW),
   .CENA(stop_A),
   .CENB(stop_A),
   .CLKA(clk),
   .CLKB(clk),
   .DBIN(delay_din)
	);	
`endif	
	

	always @ (posedge clk or negedge rst_n)
	if(!rst_n)
			delay_dout <=#DELAY 0;
	else if(clr)
			delay_dout <=#DELAY 0;
	else if(stop_A)
			delay_dout <=#DELAY delay_dout;
	else
			delay_dout <=#DELAY delay_out;	
				
endmodule