📄 pwm.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "countclk register fenpincount\[1\] register fenpincount\[7\] 271.96 MHz 3.677 ns Internal " "Info: Clock \"countclk\" has Internal fmax of 271.96 MHz between source register \"fenpincount\[1\]\" and destination register \"fenpincount\[7\]\" (period= 3.677 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.511 ns + Longest register register " "Info: + Longest register to register delay is 3.511 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fenpincount\[1\] 1 REG LC_X32_Y29_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y29_N1; Fanout = 4; REG Node = 'fenpincount\[1\]'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "" { fenpincount[1] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.419 ns) + CELL(0.183 ns) 0.602 ns reduce_nor~47 2 COMB LC_X32_Y29_N9 1 " "Info: 2: + IC(0.419 ns) + CELL(0.183 ns) = 0.602 ns; Loc. = LC_X32_Y29_N9; Fanout = 1; COMB Node = 'reduce_nor~47'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "0.602 ns" { fenpincount[1] reduce_nor~47 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.366 ns) 1.720 ns reduce_nor~0 3 COMB LC_X33_Y29_N8 5 " "Info: 3: + IC(0.752 ns) + CELL(0.366 ns) = 1.720 ns; Loc. = LC_X33_Y29_N8; Fanout = 5; COMB Node = 'reduce_nor~0'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "1.118 ns" { reduce_nor~47 reduce_nor~0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.470 ns) + CELL(0.280 ns) 2.470 ns fenpincount\[7\]~0 4 COMB LC_X32_Y29_N8 8 " "Info: 4: + IC(0.470 ns) + CELL(0.280 ns) = 2.470 ns; Loc. = LC_X32_Y29_N8; Fanout = 8; COMB Node = 'fenpincount\[7\]~0'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "0.750 ns" { reduce_nor~0 fenpincount[7]~0 } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.705 ns) 3.511 ns fenpincount\[7\] 5 REG LC_X32_Y29_N7 2 " "Info: 5: + IC(0.336 ns) + CELL(0.705 ns) = 3.511 ns; Loc. = LC_X32_Y29_N7; Fanout = 2; REG Node = 'fenpincount\[7\]'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "1.041 ns" { fenpincount[7]~0 fenpincount[7] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.534 ns 43.69 % " "Info: Total cell delay = 1.534 ns ( 43.69 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.977 ns 56.31 % " "Info: Total interconnect delay = 1.977 ns ( 56.31 % )" { } { } 0} } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "3.511 ns" { fenpincount[1] reduce_nor~47 reduce_nor~0 fenpincount[7]~0 fenpincount[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.511 ns" { fenpincount[1] reduce_nor~47 reduce_nor~0 fenpincount[7]~0 fenpincount[7] } { 0.000ns 0.419ns 0.752ns 0.470ns 0.336ns } { 0.000ns 0.183ns 0.366ns 0.280ns 0.705ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "countclk destination 2.807 ns + Shortest register " "Info: + Shortest clock path from clock \"countclk\" to destination register is 2.807 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns countclk 1 CLK PIN_L2 17 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 17; CLK Node = 'countclk'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "" { countclk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.540 ns) + CELL(0.542 ns) 2.807 ns fenpincount\[7\] 2 REG LC_X32_Y29_N7 2 " "Info: 2: + IC(1.540 ns) + CELL(0.542 ns) = 2.807 ns; Loc. = LC_X32_Y29_N7; Fanout = 2; REG Node = 'fenpincount\[7\]'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.082 ns" { countclk fenpincount[7] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.14 % " "Info: Total cell delay = 1.267 ns ( 45.14 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.540 ns 54.86 % " "Info: Total interconnect delay = 1.540 ns ( 54.86 % )" { } { } 0} } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.807 ns" { countclk fenpincount[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.807 ns" { countclk countclk~out0 fenpincount[7] } { 0.000ns 0.000ns 1.540ns } { 0.000ns 0.725ns 0.542ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "countclk source 2.807 ns - Longest register " "Info: - Longest clock path from clock \"countclk\" to source register is 2.807 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns countclk 1 CLK PIN_L2 17 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 17; CLK Node = 'countclk'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "" { countclk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.540 ns) + CELL(0.542 ns) 2.807 ns fenpincount\[1\] 2 REG LC_X32_Y29_N1 4 " "Info: 2: + IC(1.540 ns) + CELL(0.542 ns) = 2.807 ns; Loc. = LC_X32_Y29_N1; Fanout = 4; REG Node = 'fenpincount\[1\]'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.082 ns" { countclk fenpincount[1] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.14 % " "Info: Total cell delay = 1.267 ns ( 45.14 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.540 ns 54.86 % " "Info: Total interconnect delay = 1.540 ns ( 54.86 % )" { } { } 0} } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.807 ns" { countclk fenpincount[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.807 ns" { countclk countclk~out0 fenpincount[1] } { 0.000ns 0.000ns 1.540ns } { 0.000ns 0.725ns 0.542ns } } } } 0} } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.807 ns" { countclk fenpincount[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.807 ns" { countclk countclk~out0 fenpincount[7] } { 0.000ns 0.000ns 1.540ns } { 0.000ns 0.725ns 0.542ns } } } { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.807 ns" { countclk fenpincount[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.807 ns" { countclk countclk~out0 fenpincount[1] } { 0.000ns 0.000ns 1.540ns } { 0.000ns 0.725ns 0.542ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 12 -1 0 } } } 0} } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "3.511 ns" { fenpincount[1] reduce_nor~47 reduce_nor~0 fenpincount[7]~0 fenpincount[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.511 ns" { fenpincount[1] reduce_nor~47 reduce_nor~0 fenpincount[7]~0 fenpincount[7] } { 0.000ns 0.419ns 0.752ns 0.470ns 0.336ns } { 0.000ns 0.183ns 0.366ns 0.280ns 0.705ns } } } { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.807 ns" { countclk fenpincount[7] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.807 ns" { countclk countclk~out0 fenpincount[7] } { 0.000ns 0.000ns 1.540ns } { 0.000ns 0.725ns 0.542ns } } } { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.807 ns" { countclk fenpincount[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.807 ns" { countclk countclk~out0 fenpincount[1] } { 0.000ns 0.000ns 1.540ns } { 0.000ns 0.725ns 0.542ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "theout dat\[3\] countclk 3.926 ns register " "Info: tsu for register \"theout\" (data pin = \"dat\[3\]\", clock pin = \"countclk\") is 3.926 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.723 ns + Longest pin register " "Info: + Longest pin to register delay is 6.723 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns dat\[3\] 1 PIN PIN_E9 2 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_E9; Fanout = 2; PIN Node = 'dat\[3\]'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "" { dat[3] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.969 ns) + CELL(0.443 ns) 5.499 ns LessThan~127 2 COMB LC_X34_Y29_N3 1 " "Info: 2: + IC(3.969 ns) + CELL(0.443 ns) = 5.499 ns; Loc. = LC_X34_Y29_N3; Fanout = 1; COMB Node = 'LessThan~127'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "4.412 ns" { dat[3] LessThan~127 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.130 ns) 5.629 ns LessThan~122 3 COMB LC_X34_Y29_N4 1 " "Info: 3: + IC(0.000 ns) + CELL(0.130 ns) = 5.629 ns; Loc. = LC_X34_Y29_N4; Fanout = 1; COMB Node = 'LessThan~122'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "0.130 ns" { LessThan~127 LessThan~122 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 6.078 ns LessThan~105 4 COMB LC_X34_Y29_N7 1 " "Info: 4: + IC(0.000 ns) + CELL(0.449 ns) = 6.078 ns; Loc. = LC_X34_Y29_N7; Fanout = 1; COMB Node = 'LessThan~105'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "0.449 ns" { LessThan~122 LessThan~105 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.319 ns) 6.723 ns theout 5 REG LC_X34_Y29_N9 1 " "Info: 5: + IC(0.326 ns) + CELL(0.319 ns) = 6.723 ns; Loc. = LC_X34_Y29_N9; Fanout = 1; REG Node = 'theout'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "0.645 ns" { LessThan~105 theout } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.428 ns 36.11 % " "Info: Total cell delay = 2.428 ns ( 36.11 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.295 ns 63.89 % " "Info: Total interconnect delay = 4.295 ns ( 63.89 % )" { } { } 0} } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "6.723 ns" { dat[3] LessThan~127 LessThan~122 LessThan~105 theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "6.723 ns" { dat[3] dat[3]~out0 LessThan~127 LessThan~122 LessThan~105 theout } { 0.000ns 0.000ns 3.969ns 0.000ns 0.000ns 0.326ns } { 0.000ns 1.087ns 0.443ns 0.130ns 0.449ns 0.319ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "countclk destination 2.807 ns - Shortest register " "Info: - Shortest clock path from clock \"countclk\" to destination register is 2.807 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns countclk 1 CLK PIN_L2 17 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 17; CLK Node = 'countclk'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "" { countclk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.540 ns) + CELL(0.542 ns) 2.807 ns theout 2 REG LC_X34_Y29_N9 1 " "Info: 2: + IC(1.540 ns) + CELL(0.542 ns) = 2.807 ns; Loc. = LC_X34_Y29_N9; Fanout = 1; REG Node = 'theout'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.082 ns" { countclk theout } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.14 % " "Info: Total cell delay = 1.267 ns ( 45.14 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.540 ns 54.86 % " "Info: Total interconnect delay = 1.540 ns ( 54.86 % )" { } { } 0} } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.807 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.807 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.540ns } { 0.000ns 0.725ns 0.542ns } } } } 0} } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "6.723 ns" { dat[3] LessThan~127 LessThan~122 LessThan~105 theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "6.723 ns" { dat[3] dat[3]~out0 LessThan~127 LessThan~122 LessThan~105 theout } { 0.000ns 0.000ns 3.969ns 0.000ns 0.000ns 0.326ns } { 0.000ns 1.087ns 0.443ns 0.130ns 0.449ns 0.319ns } } } { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.807 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.807 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.540ns } { 0.000ns 0.725ns 0.542ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "countclk pwmout theout 6.576 ns register " "Info: tco from clock \"countclk\" to destination pin \"pwmout\" through register \"theout\" is 6.576 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "countclk source 2.807 ns + Longest register " "Info: + Longest clock path from clock \"countclk\" to source register is 2.807 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns countclk 1 CLK PIN_L2 17 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 17; CLK Node = 'countclk'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "" { countclk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.540 ns) + CELL(0.542 ns) 2.807 ns theout 2 REG LC_X34_Y29_N9 1 " "Info: 2: + IC(1.540 ns) + CELL(0.542 ns) = 2.807 ns; Loc. = LC_X34_Y29_N9; Fanout = 1; REG Node = 'theout'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.082 ns" { countclk theout } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.14 % " "Info: Total cell delay = 1.267 ns ( 45.14 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.540 ns 54.86 % " "Info: Total interconnect delay = 1.540 ns ( 54.86 % )" { } { } 0} } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.807 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.807 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.540ns } { 0.000ns 0.725ns 0.542ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.613 ns + Longest register pin " "Info: + Longest register to pin delay is 3.613 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns theout 1 REG LC_X34_Y29_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y29_N9; Fanout = 1; REG Node = 'theout'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "" { theout } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.209 ns) + CELL(2.404 ns) 3.613 ns pwmout 2 PIN PIN_F10 0 " "Info: 2: + IC(1.209 ns) + CELL(2.404 ns) = 3.613 ns; Loc. = PIN_F10; Fanout = 0; PIN Node = 'pwmout'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "3.613 ns" { theout pwmout } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns 66.54 % " "Info: Total cell delay = 2.404 ns ( 66.54 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.209 ns 33.46 % " "Info: Total interconnect delay = 1.209 ns ( 33.46 % )" { } { } 0} } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "3.613 ns" { theout pwmout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.613 ns" { theout pwmout } { 0.000ns 1.209ns } { 0.000ns 2.404ns } } } } 0} } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.807 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.807 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.540ns } { 0.000ns 0.725ns 0.542ns } } } { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "3.613 ns" { theout pwmout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.613 ns" { theout pwmout } { 0.000ns 1.209ns } { 0.000ns 2.404ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "theout dat\[7\] countclk -2.716 ns register " "Info: th for register \"theout\" (data pin = \"dat\[7\]\", clock pin = \"countclk\") is -2.716 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "countclk destination 2.807 ns + Longest register " "Info: + Longest clock path from clock \"countclk\" to destination register is 2.807 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns countclk 1 CLK PIN_L2 17 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 17; CLK Node = 'countclk'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "" { countclk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.540 ns) + CELL(0.542 ns) 2.807 ns theout 2 REG LC_X34_Y29_N9 1 " "Info: 2: + IC(1.540 ns) + CELL(0.542 ns) = 2.807 ns; Loc. = LC_X34_Y29_N9; Fanout = 1; REG Node = 'theout'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.082 ns" { countclk theout } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.14 % " "Info: Total cell delay = 1.267 ns ( 45.14 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.540 ns 54.86 % " "Info: Total interconnect delay = 1.540 ns ( 54.86 % )" { } { } 0} } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.807 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.807 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.540ns } { 0.000ns 0.725ns 0.542ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.623 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.623 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns dat\[7\] 1 PIN PIN_L7 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L7; Fanout = 1; PIN Node = 'dat\[7\]'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "" { dat[7] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm/pwm.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.816 ns) + CELL(0.075 ns) 4.978 ns LessThan~105 2 COMB LC_X34_Y29_N7 1 " "Info: 2: + IC(3.816 ns) + CELL(0.075 ns) = 4.978 ns; Loc. = LC_X34_Y29_N7; Fanout = 1; COMB Node = 'LessThan~105'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "3.891 ns" { dat[7] LessThan~105 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.319 ns) 5.623 ns theout 3 REG LC_X34_Y29_N9 1 " "Info: 3: + IC(0.326 ns) + CELL(0.319 ns) = 5.623 ns; Loc. = LC_X34_Y29_N9; Fanout = 1; REG Node = 'theout'" { } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "0.645 ns" { LessThan~105 theout } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.481 ns 26.34 % " "Info: Total cell delay = 1.481 ns ( 26.34 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.142 ns 73.66 % " "Info: Total interconnect delay = 4.142 ns ( 73.66 % )" { } { } 0} } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "5.623 ns" { dat[7] LessThan~105 theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.623 ns" { dat[7] dat[7]~out0 LessThan~105 theout } { 0.000ns 0.000ns 3.816ns 0.326ns } { 0.000ns 1.087ns 0.075ns 0.319ns } } } } 0} } { { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "2.807 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.807 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.540ns } { 0.000ns 0.725ns 0.542ns } } } { "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm/" "" "5.623 ns" { dat[7] LessThan~105 theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.623 ns" { dat[7] dat[7]~out0 LessThan~105 theout } { 0.000ns 0.000ns 3.816ns 0.326ns } { 0.000ns 1.087ns 0.075ns 0.319ns } } } } 0}
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