pwm.vhd

来自「实现PWM波型....使用VHDL语言」· VHDL 代码 · 共 38 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pwm is                        
	port(                        
		countclk: in std_logic;
		rs : in std_logic;
		dat: in std_logic_vector(7 downto 0);
		pwmout: out std_logic);--PWM信号输出
end pwm;
architecture work of pwm is    
	signal mycounter,cmpdat,fenpincount:integer range 0 to 255;
	signal theout:std_logic;
begin
process(dat)
begin
cmpdat<=conv_integer(dat);
end process;	
process(countclk,rs,cmpdat)
	begin
if (countclk'event and countclk='1') then
        	if rs='0' then
				if fenpincount=0 then
						mycounter<=mycounter+1;
						if cmpdat<mycounter then
							theout<='0';
							else
							theout<='1';
						end if;
					else
					fenpincount<=fenpincount-1;
				end if;	
			else  mycounter<=0;
			end if;	
		end if;
	end process;
	pwmout<=theout;
end work;