pwm.tan.rpt

实现PWM波型....使用VHDL语言

; N/A           ; None        ; -2.716 ns ; dat[7] ; theout         ; countclk ;
; N/A           ; None        ; -2.838 ns ; rs     ; mycounter[7]   ; countclk ;
; N/A           ; None        ; -2.838 ns ; rs     ; mycounter[6]   ; countclk ;
; N/A           ; None        ; -2.838 ns ; rs     ; mycounter[4]   ; countclk ;
; N/A           ; None        ; -2.838 ns ; rs     ; mycounter[5]   ; countclk ;
; N/A           ; None        ; -2.838 ns ; rs     ; mycounter[3]   ; countclk ;
; N/A           ; None        ; -2.838 ns ; rs     ; mycounter[2]   ; countclk ;
; N/A           ; None        ; -2.838 ns ; rs     ; mycounter[1]   ; countclk ;
; N/A           ; None        ; -2.838 ns ; rs     ; mycounter[0]   ; countclk ;
; N/A           ; None        ; -3.289 ns ; rs     ; fenpincount[2] ; countclk ;
; N/A           ; None        ; -3.289 ns ; rs     ; fenpincount[1] ; countclk ;
; N/A           ; None        ; -3.289 ns ; rs     ; fenpincount[0] ; countclk ;
; N/A           ; None        ; -3.289 ns ; rs     ; fenpincount[3] ; countclk ;
; N/A           ; None        ; -3.289 ns ; rs     ; fenpincount[4] ; countclk ;
; N/A           ; None        ; -3.289 ns ; rs     ; fenpincount[5] ; countclk ;
; N/A           ; None        ; -3.289 ns ; rs     ; fenpincount[6] ; countclk ;
; N/A           ; None        ; -3.289 ns ; rs     ; fenpincount[7] ; countclk ;
; N/A           ; None        ; -3.313 ns ; rs     ; theout         ; countclk ;
; N/A           ; None        ; -3.346 ns ; dat[6] ; theout         ; countclk ;
; N/A           ; None        ; -3.507 ns ; dat[5] ; theout         ; countclk ;
; N/A           ; None        ; -3.520 ns ; dat[4] ; theout         ; countclk ;
; N/A           ; None        ; -3.545 ns ; dat[1] ; theout         ; countclk ;
; N/A           ; None        ; -3.621 ns ; dat[0] ; theout         ; countclk ;
; N/A           ; None        ; -3.739 ns ; dat[2] ; theout         ; countclk ;
; N/A           ; None        ; -3.812 ns ; dat[3] ; theout         ; countclk ;
+---------------+-------------+-----------+--------+----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Mon May 14 22:17:08 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pwm -c pwm --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "countclk" is an undefined clock
Info: Clock "countclk" has Internal fmax of 271.96 MHz between source register "fenpincount[1]" and destination register "fenpincount[7]" (period= 3.677 ns)
    Info: + Longest register to register delay is 3.511 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y29_N1; Fanout = 4; REG Node = 'fenpincount[1]'
        Info: 2: + IC(0.419 ns) + CELL(0.183 ns) = 0.602 ns; Loc. = LC_X32_Y29_N9; Fanout = 1; COMB Node = 'reduce_nor~47'
        Info: 3: + IC(0.752 ns) + CELL(0.366 ns) = 1.720 ns; Loc. = LC_X33_Y29_N8; Fanout = 5; COMB Node = 'reduce_nor~0'
        Info: 4: + IC(0.470 ns) + CELL(0.280 ns) = 2.470 ns; Loc. = LC_X32_Y29_N8; Fanout = 8; COMB Node = 'fenpincount[7]~0'
        Info: 5: + IC(0.336 ns) + CELL(0.705 ns) = 3.511 ns; Loc. = LC_X32_Y29_N7; Fanout = 2; REG Node = 'fenpincount[7]'
        Info: Total cell delay = 1.534 ns ( 43.69 % )
        Info: Total interconnect delay = 1.977 ns ( 56.31 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "countclk" to destination register is 2.807 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 17; CLK Node = 'countclk'
            Info: 2: + IC(1.540 ns) + CELL(0.542 ns) = 2.807 ns; Loc. = LC_X32_Y29_N7; Fanout = 2; REG Node = 'fenpincount[7]'
            Info: Total cell delay = 1.267 ns ( 45.14 % )
            Info: Total interconnect delay = 1.540 ns ( 54.86 % )
        Info: - Longest clock path from clock "countclk" to source register is 2.807 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 17; CLK Node = 'countclk'
            Info: 2: + IC(1.540 ns) + CELL(0.542 ns) = 2.807 ns; Loc. = LC_X32_Y29_N1; Fanout = 4; REG Node = 'fenpincount[1]'
            Info: Total cell delay = 1.267 ns ( 45.14 % )
            Info: Total interconnect delay = 1.540 ns ( 54.86 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "theout" (data pin = "dat[3]", clock pin = "countclk") is 3.926 ns
    Info: + Longest pin to register delay is 6.723 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_E9; Fanout = 2; PIN Node = 'dat[3]'
        Info: 2: + IC(3.969 ns) + CELL(0.443 ns) = 5.499 ns; Loc. = LC_X34_Y29_N3; Fanout = 1; COMB Node = 'LessThan~127'
        Info: 3: + IC(0.000 ns) + CELL(0.130 ns) = 5.629 ns; Loc. = LC_X34_Y29_N4; Fanout = 1; COMB Node = 'LessThan~122'
        Info: 4: + IC(0.000 ns) + CELL(0.449 ns) = 6.078 ns; Loc. = LC_X34_Y29_N7; Fanout = 1; COMB Node = 'LessThan~105'
        Info: 5: + IC(0.326 ns) + CELL(0.319 ns) = 6.723 ns; Loc. = LC_X34_Y29_N9; Fanout = 1; REG Node = 'theout'
        Info: Total cell delay = 2.428 ns ( 36.11 % )
        Info: Total interconnect delay = 4.295 ns ( 63.89 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "countclk" to destination register is 2.807 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 17; CLK Node = 'countclk'
        Info: 2: + IC(1.540 ns) + CELL(0.542 ns) = 2.807 ns; Loc. = LC_X34_Y29_N9; Fanout = 1; REG Node = 'theout'
        Info: Total cell delay = 1.267 ns ( 45.14 % )
        Info: Total interconnect delay = 1.540 ns ( 54.86 % )
Info: tco from clock "countclk" to destination pin "pwmout" through register "theout" is 6.576 ns
    Info: + Longest clock path from clock "countclk" to source register is 2.807 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 17; CLK Node = 'countclk'
        Info: 2: + IC(1.540 ns) + CELL(0.542 ns) = 2.807 ns; Loc. = LC_X34_Y29_N9; Fanout = 1; REG Node = 'theout'
        Info: Total cell delay = 1.267 ns ( 45.14 % )
        Info: Total interconnect delay = 1.540 ns ( 54.86 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.613 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y29_N9; Fanout = 1; REG Node = 'theout'
        Info: 2: + IC(1.209 ns) + CELL(2.404 ns) = 3.613 ns; Loc. = PIN_F10; Fanout = 0; PIN Node = 'pwmout'
        Info: Total cell delay = 2.404 ns ( 66.54 % )
        Info: Total interconnect delay = 1.209 ns ( 33.46 % )
Info: th for register "theout" (data pin = "dat[7]", clock pin = "countclk") is -2.716 ns
    Info: + Longest clock path from clock "countclk" to destination register is 2.807 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 17; CLK Node = 'countclk'
        Info: 2: + IC(1.540 ns) + CELL(0.542 ns) = 2.807 ns; Loc. = LC_X34_Y29_N9; Fanout = 1; REG Node = 'theout'
        Info: Total cell delay = 1.267 ns ( 45.14 % )
        Info: Total interconnect delay = 1.540 ns ( 54.86 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.623 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L7; Fanout = 1; PIN Node = 'dat[7]'
        Info: 2: + IC(3.816 ns) + CELL(0.075 ns) = 4.978 ns; Loc. = LC_X34_Y29_N7; Fanout = 1; COMB Node = 'LessThan~105'
        Info: 3: + IC(0.326 ns) + CELL(0.319 ns) = 5.623 ns; Loc. = LC_X34_Y29_N9; Fanout = 1; REG Node = 'theout'
        Info: Total cell delay = 1.481 ns ( 26.34 % )
        Info: Total interconnect delay = 4.142 ns ( 73.66 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon May 14 22:17:09 2007
    Info: Elapsed time: 00:00:01