f50k.tan.qmsg

VHDL产生时钟50分频程序

{ "Info" "ITDB_TH_RESULT" "b reset clk -2.400 ns register " "Info: th for register \"b\" (data pin = \"reset\", clock pin = \"clk\") is -2.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.100 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_183 23 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 23; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns clk2 2 REG LC1_H24 14 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_H24; Fanout = 14; REG Node = 'clk2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk2 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.000 ns) 6.100 ns b 3 REG LC1_A7 17 " "Info: 3: + IC(3.100 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC1_A7; Fanout = 17; REG Node = 'b'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { clk2 b } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 26.23 % ) " "Info: Total cell delay = 1.600 ns ( 26.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns ( 73.77 % ) " "Info: Total interconnect delay = 4.500 ns ( 73.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk clk2 b } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk clk~out clk2 b } { 0.000ns 0.000ns 1.400ns 3.100ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns reset 1 PIN PIN_95 61 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_95; Fanout = 61; PIN Node = 'reset'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(1.700 ns) 8.900 ns b~23 2 COMB LC8_A7 1 " "Info: 2: + IC(4.100 ns) + CELL(1.700 ns) = 8.900 ns; Loc. = LC8_A7; Fanout = 1; COMB Node = 'b~23'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.800 ns" { reset b~23 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 9.400 ns b 3 REG LC1_A7 17 " "Info: 3: + IC(0.200 ns) + CELL(0.300 ns) = 9.400 ns; Loc. = LC1_A7; Fanout = 17; REG Node = 'b'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.500 ns" { b~23 b } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 54.26 % ) " "Info: Total cell delay = 5.100 ns ( 54.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 45.74 % ) " "Info: Total interconnect delay = 4.300 ns ( 45.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.400 ns" { reset b~23 b } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.400 ns" { reset reset~out b~23 b } { 0.000ns 0.000ns 4.100ns 0.200ns } { 0.000ns 3.100ns 1.700ns 0.300ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk clk2 b } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk clk~out clk2 b } { 0.000ns 0.000ns 1.400ns 3.100ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.400 ns" { reset b~23 b } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.400 ns" { reset reset~out b~23 b } { 0.000ns 0.000ns 4.100ns 0.200ns } { 0.000ns 3.100ns 1.700ns 0.300ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 11 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 02 16:31:13 2008 " "Info: Processing ended: Sat Aug 02 16:31:13 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}