f50k.tan.qmsg

来自「VHDL产生时钟50分频程序」· QMSG 代码 · 共 23 行 · 第 1/5 页

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "qout\[3\]\$latch " "Info: Node \"qout\[3\]\$latch\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "qout\[2\]\$latch " "Info: Node \"qout\[2\]\$latch\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "qout\[1\]\$latch " "Info: Node \"qout\[1\]\$latch\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "qout\[0\]\$latch " "Info: Node \"qout\[0\]\$latch\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 8 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}