📄 f50k.tan.qmsg

📁 VHDL产生时钟50分频程序
💻 QMSG
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1 " "Info: Detected ripple clock \"clk1\" as buffer" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 23 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk2 " "Info: Detected ripple clock \"clk2\" as buffer" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 23 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register temp\[4\] register temp\[7\] 56.5 MHz 17.7 ns Internal " "Info: Clock \"clk\" has Internal fmax of 56.5 MHz between source register \"temp\[4\]\" and destination register \"temp\[7\]\" (period= 17.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.900 ns + Longest register register " "Info: + Longest register to register delay is 15.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp\[4\] 1 REG LC1_A2 43 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A2; Fanout = 43; REG Node = 'temp\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp[4] } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.900 ns) 3.000 ns temp\[4\]~1562 2 COMB LC6_A3 7 " "Info: 2: + IC(1.100 ns) + CELL(1.900 ns) = 3.000 ns; Loc. = LC6_A3; Fanout = 7; COMB Node = 'temp\[4\]~1562'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { temp[4] temp[4]~1562 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 4.900 ns temp~1578 3 COMB LC1_A3 2 " "Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 4.900 ns; Loc. = LC1_A3; Fanout = 2; COMB Node = 'temp~1578'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { temp[4]~1562 temp~1578 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.700 ns) 6.600 ns lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 4 COMB LC8_A4 2 " "Info: 4: + IC(1.000 ns) + CELL(0.700 ns) = 6.600 ns; Loc. = LC8_A4; Fanout = 2; COMB Node = 'lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { temp~1578 lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.200 ns) 7.700 ns lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 5 COMB LC1_A6 2 " "Info: 5: + IC(0.900 ns) + CELL(0.200 ns) = 7.700 ns; Loc. = LC1_A6; Fanout = 2; COMB Node = 'lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.100 ns" { lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 7.900 ns lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 6 COMB LC2_A6 2 " "Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 7.900 ns; Loc. = LC2_A6; Fanout = 2; COMB Node = 'lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 9.500 ns lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\] 7 COMB LC3_A6 4 " "Info: 7: + IC(0.000 ns) + CELL(1.600 ns) = 9.500 ns; Loc. = LC3_A6; Fanout = 4; COMB Node = 'lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 11.400 ns LessThan0~99 8 COMB LC7_A6 1 " "Info: 8: + IC(0.200 ns) + CELL(1.700 ns) = 11.400 ns; Loc. = LC7_A6; Fanout = 1; COMB Node = 'LessThan0~99'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] LessThan0~99 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 138 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 13.600 ns LessThan0~100 9 COMB LC8_A6 6 " "Info: 9: + IC(0.200 ns) + CELL(2.000 ns) = 13.600 ns; Loc. = LC8_A6; Fanout = 6; COMB Node = 'LessThan0~100'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.200 ns" { LessThan0~99 LessThan0~100 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 138 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.300 ns) 15.900 ns temp\[7\] 10 REG LC7_A5 12 " "Info: 10: + IC(1.000 ns) + CELL(1.300 ns) = 15.900 ns; Loc. = LC7_A5; Fanout = 12; REG Node = 'temp\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.300 ns" { LessThan0~100 temp[7] } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.300 ns ( 71.07 % ) " "Info: Total cell delay = 11.300 ns ( 71.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.600 ns ( 28.93 % ) " "Info: Total interconnect delay = 4.600 ns ( 28.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.900 ns" { temp[4] temp[4]~1562 temp~1578 lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] LessThan0~99 LessThan0~100 temp[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.900 ns" { temp[4] temp[4]~1562 temp~1578 lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] LessThan0~99 LessThan0~100 temp[7] } { 0.000ns 1.100ns 0.200ns 1.000ns 0.900ns 0.000ns 0.000ns 0.200ns 0.200ns 1.000ns } { 0.000ns 1.900ns 1.700ns 0.700ns 0.200ns 0.200ns 1.600ns 1.700ns 2.000ns 1.300ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.100 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_183 23 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 23; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns clk2 2 REG LC1_H24 14 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_H24; Fanout = 14; REG Node = 'clk2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk2 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.000 ns) 6.100 ns temp\[7\] 3 REG LC7_A5 12 " "Info: 3: + IC(3.100 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC7_A5; Fanout = 12; REG Node = 'temp\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { clk2 temp[7] } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 26.23 % ) " "Info: Total cell delay = 1.600 ns ( 26.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns ( 73.77 % ) " "Info: Total interconnect delay = 4.500 ns ( 73.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk clk2 temp[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk clk~out clk2 temp[7] } { 0.000ns 0.000ns 1.400ns 3.100ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.100 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_183 23 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 23; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns clk2 2 REG LC1_H24 14 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_H24; Fanout = 14; REG Node = 'clk2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk2 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.000 ns) 6.100 ns temp\[4\] 3 REG LC1_A2 43 " "Info: 3: + IC(3.100 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC1_A2; Fanout = 43; REG Node = 'temp\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { clk2 temp[4] } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 26.23 % ) " "Info: Total cell delay = 1.600 ns ( 26.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns ( 73.77 % ) " "Info: Total interconnect delay = 4.500 ns ( 73.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk clk2 temp[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk clk~out clk2 temp[4] } { 0.000ns 0.000ns 1.400ns 3.100ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk clk2 temp[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk clk~out clk2 temp[7] } { 0.000ns 0.000ns 1.400ns 3.100ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk clk2 temp[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk clk~out clk2 temp[4] } { 0.000ns 0.000ns 1.400ns 3.100ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.900 ns" { temp[4] temp[4]~1562 temp~1578 lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] LessThan0~99 LessThan0~100 temp[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.900 ns" { temp[4] temp[4]~1562 temp~1578 lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] LessThan0~99 LessThan0~100 temp[7] } { 0.000ns 1.100ns 0.200ns 1.000ns 0.900ns 0.000ns 0.000ns 0.200ns 0.200ns 1.000ns } { 0.000ns 1.900ns 1.700ns 0.700ns 0.200ns 0.200ns 1.600ns 1.700ns 2.000ns 1.300ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk clk2 temp[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk clk~out clk2 temp[7] } { 0.000ns 0.000ns 1.400ns 3.100ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk clk2 temp[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk clk~out clk2 temp[4] } { 0.000ns 0.000ns 1.400ns 3.100ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "temp\[7\] reset clk 17.300 ns register " "Info: tsu for register \"temp\[7\]\" (data pin = \"reset\", clock pin = \"clk\") is 17.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.700 ns + Longest pin register " "Info: + Longest pin to register delay is 22.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns reset 1 PIN PIN_95 61 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_95; Fanout = 61; PIN Node = 'reset'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.200 ns) + CELL(1.900 ns) 9.200 ns temp\[1\]~1563 2 COMB LC2_A3 7 " "Info: 2: + IC(4.200 ns) + CELL(1.900 ns) = 9.200 ns; Loc. = LC2_A3; Fanout = 7; COMB Node = 'temp\[1\]~1563'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { reset temp[1]~1563 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.700 ns) 11.900 ns temp~1580 3 COMB LC3_A4 2 " "Info: 3: + IC(1.000 ns) + CELL(1.700 ns) = 11.900 ns; Loc. = LC3_A4; Fanout = 2; COMB Node = 'temp~1580'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.700 ns" { temp[1]~1563 temp~1580 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.700 ns) 12.800 ns lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 4 COMB LC5_A4 2 " "Info: 4: + IC(0.200 ns) + CELL(0.700 ns) = 12.800 ns; Loc. = LC5_A4; Fanout = 2; COMB Node = 'lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { temp~1580 lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 13.000 ns lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 5 COMB LC6_A4 2 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 13.000 ns; Loc. = LC6_A4; Fanout = 2; COMB Node = 'lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 13.200 ns lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 6 COMB LC7_A4 2 " "Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 13.200 ns; Loc. = LC7_A4; Fanout = 2; COMB Node = 'lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 13.400 ns lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 7 COMB LC8_A4 2 " "Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 13.400 ns; Loc. = LC8_A4; Fanout = 2; COMB Node = 'lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.200 ns) 14.500 ns lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 8 COMB LC1_A6 2 " "Info: 8: + IC(0.900 ns) + CELL(0.200 ns) = 14.500 ns; Loc. = LC1_A6; Fanout = 2; COMB Node = 'lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.100 ns" { lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 14.700 ns lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 9 COMB LC2_A6 2 " "Info: 9: + IC(0.000 ns) + CELL(0.200 ns) = 14.700 ns; Loc. = LC2_A6; Fanout = 2; COMB Node = 'lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 16.300 ns lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\] 10 COMB LC3_A6 4 " "Info: 10: + IC(0.000 ns) + CELL(1.600 ns) = 16.300 ns; Loc. = LC3_A6; Fanout = 4; COMB Node = 'lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 18.200 ns LessThan0~99 11 COMB LC7_A6 1 " "Info: 11: + IC(0.200 ns) + CELL(1.700 ns) = 18.200 ns; Loc. = LC7_A6; Fanout = 1; COMB Node = 'LessThan0~99'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] LessThan0~99 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 138 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 20.400 ns LessThan0~100 12 COMB LC8_A6 6 " "Info: 12: + IC(0.200 ns) + CELL(2.000 ns) = 20.400 ns; Loc. = LC8_A6; Fanout = 6; COMB Node = 'LessThan0~100'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.200 ns" { LessThan0~99 LessThan0~100 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 138 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.300 ns) 22.700 ns temp\[7\] 13 REG LC7_A5 12 " "Info: 13: + IC(1.000 ns) + CELL(1.300 ns) = 22.700 ns; Loc. = LC7_A5; Fanout = 12; REG Node = 'temp\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.300 ns" { LessThan0~100 temp[7] } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.000 ns ( 66.08 % ) " "Info: Total cell delay = 15.000 ns ( 66.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.700 ns ( 33.92 % ) " "Info: Total interconnect delay = 7.700 ns ( 33.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "22.700 ns" { reset temp[1]~1563 temp~1580 lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] LessThan0~99 LessThan0~100 temp[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "22.700 ns" { reset reset~out temp[1]~1563 temp~1580 lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] LessThan0~99 LessThan0~100 temp[7] } { 0.000ns 0.000ns 4.200ns 1.000ns 0.200ns 0.000ns 0.000ns 0.000ns 0.900ns 0.000ns 0.000ns 0.200ns 0.200ns 1.000ns } { 0.000ns 3.100ns 1.900ns 1.700ns 0.700ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.600ns 1.700ns 2.000ns 1.300ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.100 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_183 23 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 23; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns clk2 2 REG LC1_H24 14 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_H24; Fanout = 14; REG Node = 'clk2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk2 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.000 ns) 6.100 ns temp\[7\] 3 REG LC7_A5 12 " "Info: 3: + IC(3.100 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC7_A5; Fanout = 12; REG Node = 'temp\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { clk2 temp[7] } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 26.23 % ) " "Info: Total cell delay = 1.600 ns ( 26.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns ( 73.77 % ) " "Info: Total interconnect delay = 4.500 ns ( 73.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk clk2 temp[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk clk~out clk2 temp[7] } { 0.000ns 0.000ns 1.400ns 3.100ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "22.700 ns" { reset temp[1]~1563 temp~1580 lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] LessThan0~99 LessThan0~100 temp[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "22.700 ns" { reset reset~out temp[1]~1563 temp~1580 lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] LessThan0~99 LessThan0~100 temp[7] } { 0.000ns 0.000ns 4.200ns 1.000ns 0.200ns 0.000ns 0.000ns 0.000ns 0.900ns 0.000ns 0.000ns 0.200ns 0.200ns 1.000ns } { 0.000ns 3.100ns 1.900ns 1.700ns 0.700ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.600ns 1.700ns 2.000ns 1.300ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk clk2 temp[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk clk~out clk2 temp[7] } { 0.000ns 0.000ns 1.400ns 3.100ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk qout\[3\] temp\[3\] 41.600 ns register " "Info: tco from clock \"clk\" to destination pin \"qout\[3\]\" through register \"temp\[3\]\" is 41.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.100 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_183 23 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_183; Fanout = 23; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns clk2 2 REG LC1_H24 14 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_H24; Fanout = 14; REG Node = 'clk2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk2 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.000 ns) 6.100 ns temp\[3\] 3 REG LC2_A2 66 " "Info: 3: + IC(3.100 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC2_A2; Fanout = 66; REG Node = 'temp\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { clk2 temp[3] } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 26.23 % ) " "Info: Total cell delay = 1.600 ns ( 26.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns ( 73.77 % ) " "Info: Total interconnect delay = 4.500 ns ( 73.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk clk2 temp[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk clk~out clk2 temp[3] } { 0.000ns 0.000ns 1.400ns 3.100ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "34.400 ns + Longest register pin " "Info: + Longest register to pin delay is 34.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp\[3\] 1 REG LC2_A2 66 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A2; Fanout = 66; REG Node = 'temp\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp[3] } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.900 ns) + CELL(2.200 ns) 7.100 ns Mux3~434 2 COMB LC1_A47 1 " "Info: 2: + IC(4.900 ns) + CELL(2.200 ns) = 7.100 ns; Loc. = LC1_A47; Fanout = 1; COMB Node = 'Mux3~434'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.100 ns" { temp[3] Mux3~434 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.900 ns) 10.900 ns Mux3~455 3 COMB LC8_A33 1 " "Info: 3: + IC(1.900 ns) + CELL(1.900 ns) = 10.900 ns; Loc. = LC8_A33; Fanout = 1; COMB Node = 'Mux3~455'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.800 ns" { Mux3~434 Mux3~455 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(2.000 ns) 15.000 ns Mux3~456 4 COMB LC3_A8 1 " "Info: 4: + IC(2.100 ns) + CELL(2.000 ns) = 15.000 ns; Loc. = LC3_A8; Fanout = 1; COMB Node = 'Mux3~456'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.100 ns" { Mux3~455 Mux3~456 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 18.900 ns Mux3~430 5 COMB LC4_A22 1 " "Info: 5: + IC(2.200 ns) + CELL(1.700 ns) = 18.900 ns; Loc. = LC4_A22; Fanout = 1; COMB Node = 'Mux3~430'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { Mux3~456 Mux3~430 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 21.000 ns Mux3~457 6 COMB LC5_A22 2 " "Info: 6: + IC(0.200 ns) + CELL(1.900 ns) = 21.000 ns; Loc. = LC5_A22; Fanout = 2; COMB Node = 'Mux3~457'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { Mux3~430 Mux3~457 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 22.900 ns qout\[3\]\$latch 7 COMB LOOP LC1_A22 2 " "Info: 7: + IC(0.000 ns) + CELL(1.900 ns) = 22.900 ns; Loc. = LC1_A22; Fanout = 2; COMB LOOP Node = 'qout\[3\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "qout\[3\]\$latch LC1_A22 " "Info: Loc. = LC1_A22; Node \"qout\[3\]\$latch\"" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { qout[3]$latch } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { qout[3]$latch } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { Mux3~457 qout[3]$latch } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(8.600 ns) 34.400 ns qout\[3\] 8 PIN PIN_135 0 " "Info: 8: + IC(2.900 ns) + CELL(8.600 ns) = 34.400 ns; Loc. = PIN_135; Fanout = 0; PIN Node = 'qout\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.500 ns" { qout[3]$latch qout[3] } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "20.200 ns ( 58.72 % ) " "Info: Total cell delay = 20.200 ns ( 58.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.200 ns ( 41.28 % ) " "Info: Total interconnect delay = 14.200 ns ( 41.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "34.400 ns" { temp[3] Mux3~434 Mux3~455 Mux3~456 Mux3~430 Mux3~457 qout[3]$latch qout[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "34.400 ns" { temp[3] Mux3~434 Mux3~455 Mux3~456 Mux3~430 Mux3~457 qout[3]$latch qout[3] } { 0.000ns 4.900ns 1.900ns 2.100ns 2.200ns 0.200ns 0.000ns 2.900ns } { 0.000ns 2.200ns 1.900ns 2.000ns 1.700ns 1.900ns 1.900ns 8.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { clk clk2 temp[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.100 ns" { clk clk~out clk2 temp[3] } { 0.000ns 0.000ns 1.400ns 3.100ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "34.400 ns" { temp[3] Mux3~434 Mux3~455 Mux3~456 Mux3~430 Mux3~457 qout[3]$latch qout[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "34.400 ns" { temp[3] Mux3~434 Mux3~455 Mux3~456 Mux3~430 Mux3~457 qout[3]$latch qout[3] } { 0.000ns 4.900ns 1.900ns 2.100ns 2.200ns 0.200ns 0.000ns 2.900ns } { 0.000ns 2.200ns 1.900ns 2.000ns 1.700ns 1.900ns 1.900ns 8.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "reset qout\[6\] 37.000 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"qout\[6\]\" is 37.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns reset 1 PIN PIN_95 61 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_95; Fanout = 61; PIN Node = 'reset'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(1.900 ns) 9.100 ns temp\[0\]~1558 2 COMB LC1_A8 8 " "Info: 2: + IC(4.100 ns) + CELL(1.900 ns) = 9.100 ns; Loc. = LC1_A8; Fanout = 8; COMB Node = 'temp\[0\]~1558'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { reset temp[0]~1558 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(2.200 ns) 13.300 ns Mux6~587 3 COMB LC4_A14 1 " "Info: 3: + IC(2.000 ns) + CELL(2.200 ns) = 13.300 ns; Loc. = LC4_A14; Fanout = 1; COMB Node = 'Mux6~587'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.200 ns" { temp[0]~1558 Mux6~587 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(2.200 ns) 17.400 ns Mux6~588 4 COMB LC6_A2 1 " "Info: 4: + IC(1.900 ns) + CELL(2.200 ns) = 17.400 ns; Loc. = LC6_A2; Fanout = 1; COMB Node = 'Mux6~588'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.100 ns" { Mux6~587 Mux6~588 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(2.200 ns) 21.500 ns Mux6~589 5 COMB LC6_A24 1 " "Info: 5: + IC(1.900 ns) + CELL(2.200 ns) = 21.500 ns; Loc. = LC6_A24; Fanout = 1; COMB Node = 'Mux6~589'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.100 ns" { Mux6~588 Mux6~589 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 23.700 ns Mux6~591 6 COMB LC8_A24 2 " "Info: 6: + IC(0.200 ns) + CELL(2.000 ns) = 23.700 ns; Loc. = LC8_A24; Fanout = 2; COMB Node = 'Mux6~591'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.200 ns" { Mux6~589 Mux6~591 } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 25.600 ns qout\[6\]\$latch 7 COMB LOOP LC2_A24 2 " "Info: 7: + IC(0.000 ns) + CELL(1.900 ns) = 25.600 ns; Loc. = LC2_A24; Fanout = 2; COMB LOOP Node = 'qout\[6\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "qout\[6\]\$latch LC2_A24 " "Info: Loc. = LC2_A24; Node \"qout\[6\]\$latch\"" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { qout[6]$latch } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { qout[6]$latch } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { Mux6~591 qout[6]$latch } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(8.600 ns) 37.000 ns qout\[6\] 8 PIN PIN_140 0 " "Info: 8: + IC(2.800 ns) + CELL(8.600 ns) = 37.000 ns; Loc. = PIN_140; Fanout = 0; PIN Node = 'qout\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.400 ns" { qout[6]$latch qout[6] } "NODE_NAME" } } { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "24.100 ns ( 65.14 % ) " "Info: Total cell delay = 24.100 ns ( 65.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.900 ns ( 34.86 % ) " "Info: Total interconnect delay = 12.900 ns ( 34.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "37.000 ns" { reset temp[0]~1558 Mux6~587 Mux6~588 Mux6~589 Mux6~591 qout[6]$latch qout[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "37.000 ns" { reset reset~out temp[0]~1558 Mux6~587 Mux6~588 Mux6~589 Mux6~591 qout[6]$latch qout[6] } { 0.000ns 0.000ns 4.100ns 2.000ns 1.900ns 1.900ns 0.200ns 0.000ns 2.800ns } { 0.000ns 3.100ns 1.900ns 2.200ns 2.200ns 2.200ns 2.000ns 1.900ns 8.600ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
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