f50k.tan.qmsg

VHDL产生时钟50分频程序

{ "Warning" "WTDB_FOUND_COMB_LATCHES" "" "Warning: Timing Analysis found one or more latches implemented as combinational loops" { { "Warning" "WTDB_COMB_LATCH_NODE" "qout\[0\]\$latch " "Warning: Node \"qout\[0\]\$latch\" is a latch" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "qout\[1\]\$latch " "Warning: Node \"qout\[1\]\$latch\" is a latch" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "qout\[2\]\$latch " "Warning: Node \"qout\[2\]\$latch\" is a latch" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "qout\[3\]\$latch " "Warning: Node \"qout\[3\]\$latch\" is a latch" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "qout\[4\]\$latch " "Warning: Node \"qout\[4\]\$latch\" is a latch" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "qout\[5\]\$latch " "Warning: Node \"qout\[5\]\$latch\" is a latch" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "qout\[6\]\$latch " "Warning: Node \"qout\[6\]\$latch\" is a latch" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "qout\[7\]\$latch " "Warning: Node \"qout\[7\]\$latch\" is a latch" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis found one or more latches implemented as combinational loops" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "qout\[7\]\$latch " "Info: Node \"qout\[7\]\$latch\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "qout\[6\]\$latch " "Info: Node \"qout\[6\]\$latch\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "qout\[5\]\$latch " "Info: Node \"qout\[5\]\$latch\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "qout\[4\]\$latch " "Info: Node \"qout\[4\]\$latch\"" {  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "f50k.vhd" "" { Text "E:/FPGA资料/f50k/f50k/f50k.vhd" 117 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}