📄 ram.map.rpt
字号:
+-----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+------------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+------------------------------------------------------+---------------------+------------------------+
; dataout[0]$latch ; process1~0 ; yes ;
; dataout[1]$latch ; process1~0 ; yes ;
; dataout[2]$latch ; process1~0 ; yes ;
; dataout[3]$latch ; process1~0 ; yes ;
; dataout[4]$latch ; process1~0 ; yes ;
; dataout[5]$latch ; process1~0 ; yes ;
; dataout[6]$latch ; process1~0 ; yes ;
; dataout[7]$latch ; process1~0 ; yes ;
; dataout[8]$latch ; process1~0 ; yes ;
; dataout[9]$latch ; process1~0 ; yes ;
; dataout[10]$latch ; process1~0 ; yes ;
; dataout[11]$latch ; process1~0 ; yes ;
; dataout[12]$latch ; process1~0 ; yes ;
; dataout[13]$latch ; process1~0 ; yes ;
; dataout[14]$latch ; process1~0 ; yes ;
; dataout[15]$latch ; process1~0 ; yes ;
; data1~192 ; rtl~0 ; yes ;
; data1~176 ; rtl~1 ; yes ;
; data1~160 ; rtl~2 ; yes ;
; data1~208 ; rtl~3 ; yes ;
; data1~112 ; rtl~4 ; yes ;
; data1~128 ; rtl~5 ; yes ;
; data1~96 ; rtl~6 ; yes ;
; data1~144 ; rtl~7 ; yes ;
; data1~64 ; rtl~8 ; yes ;
; data1~48 ; rtl~9 ; yes ;
; data1~32 ; rtl~10 ; yes ;
; data1~80 ; rtl~11 ; yes ;
; data1~240 ; rtl~12 ; yes ;
; data1~256 ; rtl~13 ; yes ;
; data1~224 ; rtl~14 ; yes ;
; data1~272 ; rtl~15 ; yes ;
; data1~129 ; rtl~5 ; yes ;
; data1~193 ; rtl~0 ; yes ;
; data1~65 ; rtl~8 ; yes ;
; data1~257 ; rtl~13 ; yes ;
; data1~177 ; rtl~1 ; yes ;
; data1~113 ; rtl~4 ; yes ;
; data1~49 ; rtl~9 ; yes ;
; data1~241 ; rtl~12 ; yes ;
; data1~97 ; rtl~6 ; yes ;
; data1~161 ; rtl~2 ; yes ;
; data1~33 ; rtl~10 ; yes ;
; data1~225 ; rtl~14 ; yes ;
; data1~209 ; rtl~3 ; yes ;
; data1~145 ; rtl~7 ; yes ;
; data1~81 ; rtl~11 ; yes ;
; data1~273 ; rtl~15 ; yes ;
; data1~130 ; rtl~5 ; yes ;
; data1~114 ; rtl~4 ; yes ;
; data1~98 ; rtl~6 ; yes ;
; data1~146 ; rtl~7 ; yes ;
; data1~178 ; rtl~1 ; yes ;
; data1~194 ; rtl~0 ; yes ;
; data1~162 ; rtl~2 ; yes ;
; data1~210 ; rtl~3 ; yes ;
; data1~50 ; rtl~9 ; yes ;
; data1~66 ; rtl~8 ; yes ;
; data1~34 ; rtl~10 ; yes ;
; data1~82 ; rtl~11 ; yes ;
; data1~258 ; rtl~13 ; yes ;
; data1~242 ; rtl~12 ; yes ;
; data1~226 ; rtl~14 ; yes ;
; data1~274 ; rtl~15 ; yes ;
; data1~115 ; rtl~4 ; yes ;
; data1~179 ; rtl~1 ; yes ;
; data1~51 ; rtl~9 ; yes ;
; data1~243 ; rtl~12 ; yes ;
; data1~195 ; rtl~0 ; yes ;
; data1~131 ; rtl~5 ; yes ;
; data1~67 ; rtl~8 ; yes ;
; data1~259 ; rtl~13 ; yes ;
; data1~163 ; rtl~2 ; yes ;
; data1~99 ; rtl~6 ; yes ;
; data1~35 ; rtl~10 ; yes ;
; data1~227 ; rtl~14 ; yes ;
; data1~147 ; rtl~7 ; yes ;
; data1~211 ; rtl~3 ; yes ;
; data1~83 ; rtl~11 ; yes ;
; data1~275 ; rtl~15 ; yes ;
; data1~196 ; rtl~0 ; yes ;
; data1~180 ; rtl~1 ; yes ;
; data1~164 ; rtl~2 ; yes ;
; data1~212 ; rtl~3 ; yes ;
; data1~116 ; rtl~4 ; yes ;
; data1~132 ; rtl~5 ; yes ;
; data1~100 ; rtl~6 ; yes ;
; data1~148 ; rtl~7 ; yes ;
; data1~68 ; rtl~8 ; yes ;
; data1~52 ; rtl~9 ; yes ;
; data1~36 ; rtl~10 ; yes ;
; data1~84 ; rtl~11 ; yes ;
; data1~244 ; rtl~12 ; yes ;
; data1~260 ; rtl~13 ; yes ;
; data1~228 ; rtl~14 ; yes ;
; data1~276 ; rtl~15 ; yes ;
; data1~133 ; rtl~5 ; yes ;
; data1~197 ; rtl~0 ; yes ;
; data1~69 ; rtl~8 ; yes ;
; data1~261 ; rtl~13 ; yes ;
; Number of user-specified and inferred latches = 272 ; ; ;
+------------------------------------------------------+---------------------+------------------------+
Table restricted to first 100 entries. Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Sun Oct 12 14:57:00 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ram -c ram
Warning: Using design file ram.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: ram-one
Info: Found entity 1: ram
Info: Elaborating entity "ram" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at ram.vhd(27): inferring latch(es) for signal or variable "dataout", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "dataout[0]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[1]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[2]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[3]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[4]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[5]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[6]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[7]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[8]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[9]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[10]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[11]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[12]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[13]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[14]" at ram.vhd(27)
Info (10041): Inferred latch for "dataout[15]" at ram.vhd(27)
Info: Implemented 504 device resources after synthesis - the final resource count might be different
Info: Implemented 23 input pins
Info: Implemented 16 output pins
Info: Implemented 465 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
Info: Allocated 153 megabytes of memory during processing
Info: Processing ended: Sun Oct 12 14:57:05 2008
Info: Elapsed time: 00:00:05
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