ram.vhd

来自「用vhdl语言描写的存储器的读写」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ram is
port(addr:in std_logic_vector(3 downto 0);
     wr,rd:in std_logic;
       cs:in std_logic;
   datain:in std_logic_vector(15 downto 0);
  dataout:out std_logic_vector(15 downto 0));
end;

architecture one of ram is
type memory is array (0 to 15) of std_logic_vector(15 downto 0);
signal data1:memory;
signal addr1:integer range 0 to 15;
begin
addr1<=conv_integer(addr);

process(wr,cs,addr1,datain,data1)
begin
if cs='0' and wr='1' then
data1(addr1)<=datain;
end if;
end process;

process(rd,cs,addr1,data1)
begin
if cs='0' and rd='1' then
dataout<=data1(addr1);
end if;
end process;

end;