ram.tan.summary

来自「用vhdl语言描写的存储器的读写」· SUMMARY 代码 · 共 57 行

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.861 ns
From           : addr[2]
To             : dataout[11]$latch
From Clock     : --
To Clock       : rd
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 16.306 ns
From           : dataout[3]$latch
To             : dataout[3]
From Clock     : cs
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 8.360 ns
From           : datain[3]
To             : data1~35
From Clock     : --
To Clock       : addr[3]
Failed Paths   : 0

Type           : Clock Setup: 'cs'
Slack          : N/A
Required Time  : None
Actual Time    : 114.22 MHz ( period = 8.755 ns )
From           : data1~97
To             : dataout[1]$latch
From Clock     : cs
To Clock       : cs
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------