📄 display.vhd
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LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY display IS
PORT( Clock:In Std_logic;
flash:In Std_logic;
D: IN INTEGER RANGE 0 TO 9;
disp: OUT STD_LOGIC_VECTOR(0 TO 6) );
END ;
ARCHITECTURE behavior OF display IS
BEGIN
with D select
disp<="1111110" when 0,
"0110000" when 1,
"1101101" when 2,
"1111001" when 3,
"0110011" when 4,
"1011011" when 5,
"1011111" when 6,
"1110000" when 7,
"1111111" when 8,
"1111011" when 9,
"0000000" when others;
END ;
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