📄 controller.vhd
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LIBRARY IEEE;
USE IEEE.Std_Logic_1164.All;
ENTITY Controller IS
PORT
( Clock: in Std_Logic;
Hold: in Std_Logic;
CountNum: in Integer range 0 to 49;
NumA,NumB: out Integer range 0 to 25;
RedA,GreenA,YellowA: Out Std_Logic;
RedB,GreenB,YellowB: Out Std_Logic;
Flash: OUT Std_Logic
);
end;
Architecture Behavior of Controller Is
Begin
process(clock)
begin
if falling_edge(Clock) then
if hold='1' then
RedA<='1';
RedB<='1';
GreenA<='0';
GreenB<='0';
YellowA<='0';
YellowB<='0';
Flash<='1';
else
Flash<='0';
if CountNum<=19 then
NumA<=20-CountNum;
RedA<='0';
GreenA<='1';
YellowA<='0';
elsif CountNum<=24 then
NumA<=25-CountNum;
RedA<='0';
GreenA<='0';
YellowA<='1';
else
NumA<=50-CountNum;
RedA<='1';
GreenA<='0';
YellowA<='0';
end if;
if CountNum<=24 then
NumB<=25-CountNum;
RedB<='1';
GreenB<='0';
YellowB<='0';
elsif (CountNum<=44) then
NumB<=45-CountNum;
RedB<='0';
GreenB<='1';
YellowB<='0';
else
NumB<=50-CountNum;
RedB<='0';
GreenB<='0';
YellowB<='1';
end if;
end if;
end if;
end process;
end;
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