counter.tan.qmsg

verilog写的频率计程序的计数模块,

{ "Info" "ITDB_FULL_TCO_RESULT" "F_IN F_OUT F_OUT~reg0 3.900 ns register " "Info: tco from clock \"F_IN\" to destination pin \"F_OUT\" through register \"F_OUT~reg0\" is 3.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F_IN source 2.200 ns + Longest register " "Info: + Longest clock path from clock \"F_IN\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns F_IN 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'F_IN'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "" { F_IN } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/counter.v" 63 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns F_OUT~reg0 2 REG LC9 1 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC9; Fanout = 1; REG Node = 'F_OUT~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "0.400 ns" { F_IN F_OUT~reg0 } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/counter.v" 127 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "2.200 ns" { F_IN F_OUT~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN F_IN~out F_OUT~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "counter.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/counter.v" 127 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.400 ns + Longest register pin " "Info: + Longest register to pin delay is 0.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns F_OUT~reg0 1 REG LC9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC9; Fanout = 1; REG Node = 'F_OUT~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "" { F_OUT~reg0 } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/counter.v" 127 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 0.400 ns F_OUT 2 PIN PIN_8 0 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 0.400 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'F_OUT'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "0.400 ns" { F_OUT~reg0 F_OUT } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/counter.v" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns 100.00 % " "Info: Total cell delay = 0.400 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "0.400 ns" { F_OUT~reg0 F_OUT } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.400 ns" { F_OUT~reg0 F_OUT } { 0.000ns 0.000ns } { 0.000ns 0.400ns } } }  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "2.200 ns" { F_IN F_OUT~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN F_IN~out F_OUT~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "0.400 ns" { F_OUT~reg0 F_OUT } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.400 ns" { F_OUT~reg0 F_OUT } { 0.000ns 0.000ns } { 0.000ns 0.400ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "lpm_counter:Q0_rtl_0\|dffs\[0\] CLR F_IN -1.200 ns register " "Info: th for register \"lpm_counter:Q0_rtl_0\|dffs\[0\]\" (data pin = \"CLR\", clock pin = \"F_IN\") is -1.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F_IN destination 2.200 ns + Longest register " "Info: + Longest clock path from clock \"F_IN\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns F_IN 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'F_IN'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "" { F_IN } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/counter.v" 63 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns lpm_counter:Q0_rtl_0\|dffs\[0\] 2 REG LC67 45 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC67; Fanout = 45; REG Node = 'lpm_counter:Q0_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "0.400 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN F_IN~out lpm_counter:Q0_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns CLR 1 PIN PIN_81 57 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_81; Fanout = 57; PIN Node = 'CLR'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "" { CLR } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/counter.v" 62 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(2.800 ns) 5.000 ns lpm_counter:Q0_rtl_0\|dffs\[0\] 2 REG LC67 45 " "Info: 2: + IC(2.000 ns) + CELL(2.800 ns) = 5.000 ns; Loc. = LC67; Fanout = 45; REG Node = 'lpm_counter:Q0_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "4.800 ns" { CLR lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 60.00 % " "Info: Total cell delay = 3.000 ns ( 60.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 40.00 % " "Info: Total interconnect delay = 2.000 ns ( 40.00 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "5.000 ns" { CLR lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.000 ns" { CLR CLR~out lpm_counter:Q0_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 0.200ns 2.800ns } } }  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN F_IN~out lpm_counter:Q0_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } { "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/counter/" "" "5.000 ns" { CLR lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.000 ns" { CLR CLR~out lpm_counter:Q0_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 0.200ns 2.800ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 10 20:34:41 2006 " "Info: Processing ended: Mon Jul 10 20:34:41 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}