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Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledNo errors in compilationAnalysis of file <"bianma.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <bianma>.Module <bianma> is correct for synthesis. Analyzing module <DFF>.Module <DFF> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <DFF>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Q>. Summary: inferred 1 D-type flip-flop(s).Unit <DFF> synthesized.Synthesizing Unit <bianma>. Related source file is "212bianmaqi.v".WARNING:Xst:1306 - Output <Dout> is never assigned. Found 1-bit register for signal <Dout1>. Found 1-bit register for signal <Dout2>. Found 1-bit xor2 for signal <$n0000> created at line 52. Found 1-bit xor2 for signal <$n0001> created at line 53. Summary: inferred 2 D-type flip-flop(s). inferred 2 Xor(s).Unit <bianma> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 4 1-bit register : 4# Xors : 2 1-bit xor2 : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledNo errors in compilationAnalysis of file <"bianma.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <bianma>.Module <bianma> is correct for synthesis. Analyzing module <DFF>.Module <DFF> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <DFF>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Q>. Summary: inferred 1 D-type flip-flop(s).Unit <DFF> synthesized.Synthesizing Unit <bianma>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Dout1>. Found 1-bit register for signal <Dout2>. Found 1-bit xor2 for signal <$n0000> created at line 52. Found 1-bit xor2 for signal <$n0001> created at line 53. Summary: inferred 2 D-type flip-flop(s). inferred 2 Xor(s).Unit <bianma> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 4 1-bit register : 4# Xors : 2 1-bit xor2 : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:247 - "212bianmaqi.v" line 52 Reference to scalar wire 'Dout1' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 52 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "212bianmaqi.v" line 53 Reference to scalar wire 'Dout2' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 53 Illegal left hand side of blocking assignmentAnalysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 4 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 38 unexpected token: ','Module <bianma> compiledAnalysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:247 - "212bianmaqi.v" line 52 Reference to scalar wire 'Dout1' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 52 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "212bianmaqi.v" line 53 Reference to scalar wire 'Dout2' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 53 Illegal left hand side of blocking assignmentAnalysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 4 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 38 unexpected token: ','Module <bianma> compiledAnalysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 37 unexpected token: 'Dout1'ERROR:HDLCompilers:26 - "212bianmaqi.v" line 38 unexpected token: 'Dout2'Module <bianma> compiledAnalysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 2 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:247 - "212bianmaqi.v" line 53 Reference to scalar wire 'Dout1' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 53 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "212bianmaqi.v" line 54 Reference to scalar wire 'Dout2' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 54 Illegal left hand side of blocking assignmentAnalysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 4 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:247 - "212bianmaqi.v" line 53 Reference to scalar wire 'Dout1' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 53 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "212bianmaqi.v" line 54 Reference to scalar wire 'Dout2' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 54 Illegal left hand side of blocking assignmentAnalysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 4 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 53 unexpected token: 'xor'Module <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 53 expecting 'endmodule', found '('Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 2 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
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