_primary.vhd

来自「一个完整的viterbi(2,1,7)编码程序」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity bianma is
    port(
        CLK1            : in     vl_logic;
        Din             : in     vl_logic;
        Dout1           : out    vl_logic;
        Dout2           : out    vl_logic;
        Dout            : out    vl_logic
    );
end bianma;