📄 __projnav.log
字号:
Macro Statistics# Registers : 3 1-bit register : 3==================================================================================================================================================* Low Level Synthesis *=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledNo errors in compilationAnalysis of file <"bianma.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <bianma>.Module <bianma> is correct for synthesis. Analyzing module <DFF>.Module <DFF> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <DFF>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Q>. Summary: inferred 1 D-type flip-flop(s).Unit <DFF> synthesized.Synthesizing Unit <bianma>. Related source file is "212bianmaqi.v".WARNING:Xst:646 - Signal <Dout1> is assigned but never used.WARNING:Xst:646 - Signal <Dout2> is assigned but never used.WARNING:Xst:2110 - Clock of register <Dout> seems to be also used in the data or control logic of that element. Found 1-bit register for signal <Dout>. Found 1-bit xor3 for signal <$old_Dout1_1>. Found 1-bit adder for signal <$old_Dout2_2>. Summary: inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtractor(s).Unit <bianma> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 1 1-bit adder : 1# Registers : 3 1-bit register : 3# Xors : 1 1-bit xor3 : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 52 unexpected token: 'xor'Module <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 52 expecting 'endmodule', found '('Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 2 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledNo errors in compilationAnalysis of file <"bianma.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <bianma>.Module <bianma> is correct for synthesis. Analyzing module <DFF>.Module <DFF> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <DFF>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Q>. Summary: inferred 1 D-type flip-flop(s).Unit <DFF> synthesized.Synthesizing Unit <bianma>. Related source file is "212bianmaqi.v".WARNING:Xst:646 - Signal <Dout1> is assigned but never used.WARNING:Xst:646 - Signal <Dout2> is assigned but never used.WARNING:Xst:2110 - Clock of register <Dout> seems to be also used in the data or control logic of that element. Found 1-bit register for signal <Dout>. Found 1-bit xor2 for signal <$old_Dout1_1>. Found 1-bit xor2 for signal <$old_Dout2_2>. Summary: inferred 1 D-type flip-flop(s). inferred 2 Xor(s).Unit <bianma> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 3 1-bit register : 3# Xors : 2 1-bit xor2 : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 61 expecting 'end', found 'endmodule'Module <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 62 expecting 'endmodule', found 'EOF'Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 2 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledNo errors in compilationAnalysis of file <"bianma.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <bianma>.Module <bianma> is correct for synthesis. Analyzing module <DFF>.Module <DFF> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <DFF>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Q>. Summary: inferred 1 D-type flip-flop(s).Unit <DFF> synthesized.Synthesizing Unit <bianma>. Related source file is "212bianmaqi.v".WARNING:Xst:1306 - Output <Dout> is never assigned.WARNING:Xst:646 - Signal <Dout1> is assigned but never used.WARNING:Xst:646 - Signal <Dout2> is assigned but never used.Unit <bianma> synthesized.WARNING:Xst:524 - All outputs of the instance <ff1> of the block <DFF> are unconnected in block <bianma>. This instance will be removed from the design along with all underlying logicWARNING:Xst:524 - All outputs of the instance <ff2> of the block <DFF> are unconnected in block <bianma>. This instance will be removed from the design along with all underlying logic=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledERROR:HDLCompilers:207 - "212bianmaqi.v" line 36 Signal 'Dout' is not referenced in the module port listERROR:HDLCompilers:208 - "212bianmaqi.v" line 34 Port reference 'Dout1' was not declared as input, inout or outputERROR:HDLCompilers:208 - "212bianmaqi.v" line 34 Port reference 'Dout2' was not declared as input, inout or outputModule <bianma> compiledAnalysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 3 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledERROR:HDLCompilers:208 - "212bianmaqi.v" line 34 Port reference 'Dout1' was not declared as input, inout or outputERROR:HDLCompilers:208 - "212bianmaqi.v" line 34 Port reference 'Dout2' was not declared as input, inout or outputModule <bianma> compiledAnalysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 2 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -