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=========================================================================* HDL Analysis *=========================================================================Analyzing top module <bianma>.Module <bianma> is correct for synthesis. Analyzing module <DFF>.Module <DFF> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <DFF>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Q>. Summary: inferred 1 D-type flip-flop(s).Unit <DFF> synthesized.Synthesizing Unit <bianma>. Related source file is "212bianmaqi.v".WARNING:Xst:646 - Signal <Dout1> is assigned but never used.WARNING:Xst:646 - Signal <Dout2> is assigned but never used. Found 1-bit register for signal <Dout>. Summary: inferred 1 D-type flip-flop(s).Unit <bianma> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 3 1-bit register : 3==================================================================================================================================================* Low Level Synthesis *=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 55 expecting 'endmodule', found 'if'Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledNo errors in compilationAnalysis of file <"bianma.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <bianma>.WARNING:Xst:916 - "212bianmaqi.v" line 58: Delay is ignored for synthesis.Module <bianma> is correct for synthesis. Analyzing module <DFF>.Module <DFF> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <DFF>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Q>. Summary: inferred 1 D-type flip-flop(s).Unit <DFF> synthesized.Synthesizing Unit <bianma>. Related source file is "212bianmaqi.v".WARNING:Xst:647 - Input <CLK2> is never used.WARNING:Xst:646 - Signal <Dout1> is assigned but never used.WARNING:Xst:646 - Signal <Dout2> is assigned but never used. Found 1-bit register for signal <Dout>. Summary: inferred 1 D-type flip-flop(s).Unit <bianma> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 3 1-bit register : 3==================================================================================================================================================* Low Level Synthesis *=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledNo errors in compilationAnalysis of file <"bianma.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <bianma>.WARNING:Xst:916 - "212bianmaqi.v" line 56: Delay is ignored for synthesis.WARNING:Xst:916 - "212bianmaqi.v" line 58: Delay is ignored for synthesis.Module <bianma> is correct for synthesis. Analyzing module <DFF>.Module <DFF> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <DFF>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Q>. Summary: inferred 1 D-type flip-flop(s).Unit <DFF> synthesized.Synthesizing Unit <bianma>. Related source file is "212bianmaqi.v".WARNING:Xst:647 - Input <CLK2> is never used.WARNING:Xst:646 - Signal <Dout1> is assigned but never used.WARNING:Xst:646 - Signal <Dout2> is assigned but never used. Found 1-bit register for signal <Dout>. Summary: inferred 1 D-type flip-flop(s).Unit <bianma> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 3 1-bit register : 3==================================================================================================================================================* Low Level Synthesis *=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 56 expecting 'endmodule', found 'if'Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledNo errors in compilationAnalysis of file <"bianma.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <bianma>.Module <bianma> is correct for synthesis. Analyzing module <DFF>.Module <DFF> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <DFF>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Q>. Summary: inferred 1 D-type flip-flop(s).Unit <DFF> synthesized.Synthesizing Unit <bianma>. Related source file is "212bianmaqi.v".WARNING:Xst:646 - Signal <Dout1> is assigned but never used.WARNING:Xst:646 - Signal <Dout2> is assigned but never used.WARNING:Xst:2110 - Clock of register <Dout> seems to be also used in the data or control logic of that element. Found 1-bit register for signal <Dout>. Summary: inferred 1 D-type flip-flop(s).Unit <bianma> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 3 1-bit register : 3==================================================================================================================================================* Low Level Synthesis *=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledNo errors in compilationAnalysis of file <"bianma.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <bianma>.Module <bianma> is correct for synthesis. Analyzing module <DFF>.Module <DFF> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <DFF>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Q>. Summary: inferred 1 D-type flip-flop(s).Unit <DFF> synthesized.Synthesizing Unit <bianma>. Related source file is "212bianmaqi.v".WARNING:Xst:646 - Signal <Dout1> is assigned but never used.WARNING:Xst:646 - Signal <Dout2> is assigned but never used.WARNING:Xst:2110 - Clock of register <Dout> seems to be also used in the data or control logic of that element. Found 1-bit register for signal <Dout>. Summary: inferred 1 D-type flip-flop(s).Unit <bianma> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis Report⌨️ 快捷键说明
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