📄 __projnav.log
字号:
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledNo errors in compilationAnalysis of file <"bianma.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <bianma>.Module <bianma> is correct for synthesis. Analyzing module <DFF>.Module <DFF> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <DFF>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Q>. Summary: inferred 1 D-type flip-flop(s).Unit <DFF> synthesized.Synthesizing Unit <bianma>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Dout1>. Found 1-bit register for signal <Dout2>. Summary: inferred 2 D-type flip-flop(s).Unit <bianma> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 4 1-bit register : 4==================================================================================================================================================* Low Level Synthesis *=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledNo errors in compilationAnalysis of file <"bianma.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <bianma>.Module <bianma> is correct for synthesis. Analyzing module <DFF>.Module <DFF> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <DFF>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Q>. Summary: inferred 1 D-type flip-flop(s).Unit <DFF> synthesized.Synthesizing Unit <bianma>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Dout1>. Found 1-bit register for signal <Dout2>. Summary: inferred 2 D-type flip-flop(s).Unit <bianma> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 4 1-bit register : 4==================================================================================================================================================* Low Level Synthesis *=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:247 - "212bianmaqi.v" line 50 Reference to scalar wire 'Dout1' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 50 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "212bianmaqi.v" line 51 Reference to scalar wire 'Dout2' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 51 Illegal left hand side of blocking assignmentAnalysis of file <"bianma.prj"> failed.--> Total memory usage is 77004 kilobytesNumber of errors : 4 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledNo errors in compilationAnalysis of file <"bianma.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <bianma>.Module <bianma> is correct for synthesis. Analyzing module <DFF>.Module <DFF> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <DFF>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Q>. Summary: inferred 1 D-type flip-flop(s).Unit <DFF> synthesized.Synthesizing Unit <bianma>. Related source file is "212bianmaqi.v". Found 1-bit register for signal <Dout1>. Found 1-bit register for signal <Dout2>. Summary: inferred 2 D-type flip-flop(s).Unit <bianma> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 4 1-bit register : 4==================================================================================================================================================* Low Level Synthesis *=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledERROR:HDLCompilers:28 - "212bianmaqi.v" line 50 'Dout1' has not been declaredERROR:HDLCompilers:28 - "212bianmaqi.v" line 51 'Dout2' has not been declaredERROR:HDLCompilers:28 - "212bianmaqi.v" line 55 'Dout1' has not been declaredERROR:HDLCompilers:28 - "212bianmaqi.v" line 58 'Dout2' has not been declaredModule <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 59 expecting 'endmodule', found 'end'Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 5 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 60 expecting 'endmodule', found 'end'Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:247 - "212bianmaqi.v" line 51 Reference to scalar wire 'Dout1' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 51 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "212bianmaqi.v" line 52 Reference to scalar wire 'Dout2' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 52 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "212bianmaqi.v" line 56 Reference to scalar wire 'Dout' is not a legal reg or variable lvalueERROR:HDLCompilers:42 - "212bianmaqi.v" line 56 Illegal left hand side of procedural assignERROR:HDLCompilers:247 - "212bianmaqi.v" line 59 Reference to scalar wire 'Dout' is not a legal reg or variable lvalueERROR:HDLCompilers:42 - "212bianmaqi.v" line 59 Illegal left hand side of procedural assignAnalysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 8 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 60 expecting 'endmodule', found 'end'Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiled⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -