ddr_data_path.srr

DDR（双速率）SDRAM控制器参考设计verilog代码

data_path1.dq2[1]     apex20k_lcell_ff     regout     data_path1.dq2[1]     500.5       494.1
data_path1.dq2[2]     apex20k_lcell_ff     regout     data_path1.dq2[2]     500.5       494.1
data_path1.dq2[3]     apex20k_lcell_ff     regout     data_path1.dq2[3]     500.5       494.1
data_path1.dq2[4]     apex20k_lcell_ff     regout     data_path1.dq2[4]     500.5       494.1
data_path1.dq2[5]     apex20k_lcell_ff     regout     data_path1.dq2[5]     500.5       494.1
data_path1.dq2[6]     apex20k_lcell_ff     regout     data_path1.dq2[6]     500.5       494.1
data_path1.dq2[7]     apex20k_lcell_ff     regout     data_path1.dq2[7]     500.5       494.1
data_path1.dq2[8]     apex20k_lcell_ff     regout     data_path1.dq2[8]     500.5       494.1
data_path1.dq2[9]     apex20k_lcell_ff     regout     data_path1.dq2[9]     500.5       494.1
=============================================================================================

End Points for Paths with Slack Worse than 494.7 ns : 

                                              Required          
Instance     Type     Pin       Net           Time         Slack
----------------------------------------------------------------
DQ[63:0]     Port     DQ[0]     DQ_tri[0]     1000.0       494.1
DQ[63:0]     Port     DQ[1]     DQ_tri[1]     1000.0       494.1
DQ[63:0]     Port     DQ[2]     DQ_tri[2]     1000.0       494.1
DQ[63:0]     Port     DQ[3]     DQ_tri[3]     1000.0       494.1
DQ[63:0]     Port     DQ[4]     DQ_tri[4]     1000.0       494.1
DQ[63:0]     Port     DQ[5]     DQ_tri[5]     1000.0       494.1
DQ[63:0]     Port     DQ[6]     DQ_tri[6]     1000.0       494.1
DQ[63:0]     Port     DQ[7]     DQ_tri[7]     1000.0       494.1
DQ[63:0]     Port     DQ[8]     DQ_tri[8]     1000.0       494.1
DQ[63:0]     Port     DQ[9]     DQ_tri[9]     1000.0       494.1
================================================================

A Critical Path with worst case slack = 494.1 ns:  

The start point of this path has a clock (CLK200_inferred_clock [rising]) that has an offset of 500.0ns with
respect to the start of the period of the destination clock (CLK200_inferred_clock [falling])
Instance/Net                               Pin        Pin     Arrival     Delta     Fan
Name                  Type                 Name       Dir     Time        Delay     Out
---------------------------------------------------------------------------------------
data_path1.dq2[0]     apex20k_lcell_ff     regout     Out     500.5       0.5          
data_path1.dq2[0]     Net                                                           1  
DQ_tri[0]             apex20k_io           datain     In      500.5                    
DQ_tri[0]             apex20k_io           padio      Out     505.9       5.4          
DQ_tri[0]             Net                                                           2  
DQ[63:0]              Port                 DQ[0]      In      505.9                    
=======================================================================================
This path has no setup requirement


		Detailed Timing Report for  clock : CLK100_inferred_clock 
		*******************************************
Requested Period 	  1000.0 ns
Estimated Period 	  501.8 ns
Worst Slack 	 	 498.2 ns

Start Points for Paths with Slack Worse than 498.8 ns : 

                                                                                      Arrival          
Instance                   Type                 Pin        Net                        Time        Slack
-------------------------------------------------------------------------------------------------------
command1.OE                apex20k_lcell_ff     regout     command1.OE                0.9         498.2
data_path1.din1x_h1[0]     apex20k_lcell_ff     regout     data_path1.din1x_h1[0]     500.5       498.6
data_path1.din1x_h1[1]     apex20k_lcell_ff     regout     data_path1.din1x_h1[1]     500.5       498.6
data_path1.din1x_h1[2]     apex20k_lcell_ff     regout     data_path1.din1x_h1[2]     500.5       498.6
data_path1.din1x_h1[3]     apex20k_lcell_ff     regout     data_path1.din1x_h1[3]     500.5       498.6
data_path1.din1x_h1[4]     apex20k_lcell_ff     regout     data_path1.din1x_h1[4]     500.5       498.6
data_path1.din1x_h1[5]     apex20k_lcell_ff     regout     data_path1.din1x_h1[5]     500.5       498.6
data_path1.din1x_h1[6]     apex20k_lcell_ff     regout     data_path1.din1x_h1[6]     500.5       498.6
data_path1.din1x_h1[7]     apex20k_lcell_ff     regout     data_path1.din1x_h1[7]     500.5       498.6
data_path1.din1x_h1[8]     apex20k_lcell_ff     regout     data_path1.din1x_h1[8]     500.5       498.6
=======================================================================================================

End Points for Paths with Slack Worse than 498.8 ns : 

                                                                                     Required          
Instance                   Type                 Pin       Net                        Time         Slack
-------------------------------------------------------------------------------------------------------
data_path4.ioen            apex20k_lcell_ff     dataa     command1.OE                999.1        498.2
data_path1.din1x_h2[0]     apex20k_lcell_ff     dataa     data_path1.din1x_h1[0]     999.1        498.6
data_path1.din1x_h2[1]     apex20k_lcell_ff     dataa     data_path1.din1x_h1[1]     999.1        498.6
data_path1.din1x_h2[2]     apex20k_lcell_ff     dataa     data_path1.din1x_h1[2]     999.1        498.6
data_path1.din1x_h2[3]     apex20k_lcell_ff     dataa     data_path1.din1x_h1[3]     999.1        498.6
data_path1.din1x_h2[4]     apex20k_lcell_ff     dataa     data_path1.din1x_h1[4]     999.1        498.6
data_path1.din1x_h2[5]     apex20k_lcell_ff     dataa     data_path1.din1x_h1[5]     999.1        498.6
data_path1.din1x_h2[6]     apex20k_lcell_ff     dataa     data_path1.din1x_h1[6]     999.1        498.6
data_path1.din1x_h2[7]     apex20k_lcell_ff     dataa     data_path1.din1x_h1[7]     999.1        498.6
data_path1.din1x_h2[8]     apex20k_lcell_ff     dataa     data_path1.din1x_h1[8]     999.1        498.6
=======================================================================================================

A Critical Path with worst case slack = 498.2 ns:  

The start point of this path has a clock (CLK100_inferred_clock [rising]) that has an offset of 500.0ns with
respect to the start of the period of the destination clock (CLK100_inferred_clock [falling])
Instance/Net                             Pin        Pin     Arrival     Delta     Fan
Name                Type                 Name       Dir     Time        Delay     Out
-------------------------------------------------------------------------------------
command1.OE         apex20k_lcell_ff     regout     Out     500.9       0.9          
command1.OE         Net                                                           3  
data_path4.ioen     apex20k_lcell_ff     dataa      In      500.9                    
=====================================================================================
Setup requirement on this path is 0.9 ns. 


		 ##### END TIMING REPORT #####


---------------------------------------
Resource Usage Report

Synplify is performing all technology mapping.

Design view:work.ddr_sdram(verilog)
Selecting part ep20k400efc672-1x

@N:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_sdram.v":110:5:110:9|Found black box instance work.ddr_sdram(verilog)-PLL_1 of view:work.pll1(verilog) without an altera_area attribute.  Reports will not include any lcells for this instance 
I/O ATOMs:       400

Logic resources:  1410 ATOMs of 16640 ( 8%)
ATOM count by mode:
  normal:       1394
  arithmetic:   0
  counter:      15
  qfbk_counter: 16

Black-boxes:    1

ATOMs using regout pin: 1387
  also using enable pin: 72
  also using combout pin: 1
  with no input combinational logic: 1102 (uses cell for routing)

ATOMs using combout pin: 20
ATOMs using cascin pin: 5

Number of Inputs on ATOMs: 4572
Number of Nets:   2085

Writing .vqm output for Quartus
Writing Cross reference file for Quartus to d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.xrf
Found clock CLK200_inferred_clock with period 1000ns
Found clock CLK100_inferred_clock with period 1000ns
Found clock CLK with period 10ns
Mapper successful!
Process took 7.291 seconds realtime, 7.29 seconds cputime