📄 ddr_data_path.srr
字号:
DQ[25] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[26] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[27] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[28] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[29] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[30] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[31] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[32] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[33] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[34] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[35] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[36] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[37] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[38] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[39] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[40] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[41] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[42] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[43] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[44] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[45] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[46] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[47] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[48] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[49] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[50] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[51] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[52] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[53] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[54] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[55] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[56] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[57] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[58] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[59] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[60] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[61] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[62] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
DQ[63] CLK200_inferred_clock [falling] 0.0 0.0 994.6 994.6
RESET_N CLK100_inferred_clock [rising] 0.0 0.0 990.0 990.0
=================================================================================================
Output Ports:
Port Reference User Arrival Required
Name Clock Constraint Time Time Slack
--------------------------------------------------------------------------------------------------
BA[0] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
BA[1] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
CAS_N CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
CKE CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
CMDACK CLK100_inferred_clock [rising] 0.0 6.1 1000.0 993.9
CS_N[0] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
CS_N[1] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[0] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[1] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[2] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[3] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[4] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[5] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[6] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[7] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[8] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[9] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[10] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[11] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[12] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[13] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[14] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[15] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[16] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[17] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[18] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[19] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[20] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[21] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[22] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[23] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[24] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[25] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[26] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[27] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[28] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[29] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[30] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[31] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[32] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[33] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[34] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[35] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[36] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[37] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[38] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[39] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[40] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[41] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[42] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[43] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[44] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[45] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[46] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[47] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[48] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[49] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[50] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[51] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[52] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[53] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[54] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[55] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[56] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[57] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[58] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[59] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[60] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[61] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[62] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[63] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[64] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[65] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[66] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[67] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[68] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[69] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[70] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[71] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[72] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[73] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[74] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[75] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[76] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[77] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[78] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[79] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[80] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[81] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[82] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[83] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[84] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[85] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[86] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[87] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[88] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[89] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
DATAOUT[90] CLK100_inferred_clock [rising] 0.0 5.9 1000.0 994.1
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -