ddr_sdram_rm.tcl

DDR（双速率）SDRAM控制器参考设计verilog代码

if {[cmp get_assignment_value "" "" "" ROOT] != ""} {
  cmp remove_assignment "" "" "" ROOT ""
}
if {[cmp get_assignment_value "" "" "" FAMILY] !=  ""} {
  cmp remove_assignment "" "" "" FAMILY ""
}
if {[cmp get_assignment_value "ddr_sdram" "" "" DEVICE] !=  ""} {
  cmp remove_assignment "ddr_sdram" "" "" DEVICE ""
}
if {[project get_assignment_value "ddr_sdram" "" "" "|CLK" "GLOBAL_SIGNAL"] !=  ""} {
  project remove_assignment "ddr_sdram" "" "" "|CLK" "GLOBAL_SIGNAL" ""
}
if {[project get_assignment_value "" "CLK_setting" "" "" "FMAX_REQUIREMENT"] != ""} {
  project remove_assignment "" "CLK_setting" "" "" "FMAX_REQUIREMENT" ""
}
if {[project get_assignment_value "ddr_sdram" "" "" "|CLK" "USE_CLOCK_SETTINGS"] != ""} {
  project remove_assignment "ddr_sdram" "" "" "|CLK" "USE_CLOCK_SETTINGS" ""
}
if {[project get_assignment_value "" "CLK_setting" "" "" "DUTY_CYCLE"] != ""} {
  project remove_assignment "" "CLK_setting" "" "" "DUTY_CYCLE" ""
}