ddr_sdram.srm

DDR（双速率）SDRAM控制器参考设计verilog代码

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V"\8:b[sFC#O0\0NDC\sNDFbOs\C#8\8ssCCDN\#CP44_\M#$0#ECH##\$DMbH0OH$D\bDP43"y;RVCHDRVd
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R:"8\Fbs[0CO#D\N0NCs\ODbF#sC\s88\DsCCCN#\_P44$\#MC0E#\H##b$MDHHO08$\8Os_FNllMP83"y;RVCHDRV6
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R:"8\Fbs[0CO#D\N0NCs\ODbF#sC\s88\DsCCCN#\_P44$\#MC0E#\H##b$MDHHO0b$\NlsN#"3P;VRyHRDC.R
V"\8:b[sFC#O0\0NDC\sNDFbOs\C#8\8ssCCDN\#CP44_\M#$0#ECH##\$DMbH0OH$D\bDP43"y;RVCHDRVd
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