ddr_sdram.sdc

DDR（双速率）SDRAM控制器参考设计verilog代码

# Synplicity, Inc. constraint file
# D:\Projects\altera\lpcores\ddr\release\V1_1\synthesis\synplicity\ddr_sdram.sdc
# Written on Sat May 20 12:22:07 2000
# by Synplify 5.3.1 Scope Editor

#
# Clocks
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define_clock          {CLK} -freq 100.000

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# Clock to Clock
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# Inputs/Outputs
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# Registers
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# Multi-Cycle Paths
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# False Paths
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# Attributes
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# Other Constraints
#