ddr_sdram.sdc

来自「DDR（双速率）SDRAM控制器参考设计verilog代码」· SDC 代码 · 共 38 行

# Synplicity, Inc. constraint file
# D:\Projects\altera\lpcores\ddr\release\V1_1\synthesis\synplicity\ddr_sdram.sdc
# Written on Sat May 20 12:22:07 2000
# by Synplify 5.3.1 Scope Editor

#
# Clocks
#
define_clock          {CLK} -freq 100.000

#
# Clock to Clock
#

#
# Inputs/Outputs
#

#
# Registers
#

#
# Multi-Cycle Paths
#

#
# False Paths
#

#
# Attributes
#

#
# Other Constraints
#