readme.txt

来自「DDR（双速率）SDRAM控制器参考设计verilog代码」· 文本 代码 · 共 9 行

Directory: \simulation

This directory contains the verilog testbench and the modelsim ini file for the 
DDR SDRAM controller reference design.  The \work directory contains a precompiled
library of the complete design.  In order to modify the design and re-simulate, simply
copy the source files from \source and \model into this directory and re-compile the
design.