_primary.vhd

DDR（双速率）SDRAM控制器参考设计verilog代码

library verilog;
use verilog.vl_types.all;
entity altclklock is
    generic(
        inclock_period  : integer := 10000;
        inclock_settings: string  := "UNUSED";
        valid_lock_cycles: integer := 3;
        invalid_lock_cycles: integer := 3;
        valid_lock_multiplier: integer := 1;
        invalid_lock_multiplier: integer := 1;
        operation_mode  : string  := "NORMAL";
        clock0_boost    : integer := 1;
        clock0_divide   : integer := 1;
        clock1_boost    : integer := 2;
        clock1_divide   : integer := 1;
        clock0_settings : string  := "UNUSED";
        clock1_settings : string  := "UNUSED";
        outclock_phase_shift: integer := 0
    );
    port(
        inclock         : in     vl_logic;
        locked          : out    vl_logic;
        clock0          : out    vl_logic;
        clock1          : out    vl_logic
    );
end altclklock;