mt46v4m16.v

来自「DDR（双速率）SDRAM控制器参考设计verilog代码」· Verilog 代码 · 共 30 行

/****************************************************************************************
*
*    File Name:  MT46V4M16.V  
*      Version:  0.0f
*         Date:  May 20th, 1999
*        Model:  BUS Functional
*    Simulator:  Model Technology (PC version 5.2e PE)
*
* Dependencies:  None
*
*       Author:  Son P. Huynh
*        Email:  [e-mail]
*        Phone:  [phone]
*      Company:  Micron Technology, Inc.
*  Part Number:  MT46V4M16 (1Meg x 16 x 4 Banks)
*
*  Description:  Micron 64Mb SDRAM DDR (Double Data Rate)
*
*   Limitation:  - Doesn't check for 4096-cycle refresh
*
*         Note:  - Set simulator resolution to "ps" accuracy
*                - Set Debug = 0 to disable $display messages
*                - Model assume Clk and Clk# crossing at both edge
*
*   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
*                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
*                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
*                Copyright