disp.vhd

多功能数字钟的设计

library ieee; 
use ieee.std_logic_1164.all; 
  
entity disp is 
port(d:in std_logic_vector(3 downto 0); 
q:out std_logic_vector(7 downto 0)); 
end disp; 
  
architecture disp_arc of disp is 
begin 
process(d) 
begin 
case d is 
when "0000"=>q<="11000000"; 
when "0001"=>q<="11111001"; 
when "0010"=>q<="10100100"; 
when "0011"=>q<="10110000"; 
when "0100"=>q<="10011001"; 
when "0101"=>q<="10010010"; 
when "0110"=>q<="10000010"; 
when "0111"=>q<="11011000"; 
when "1000"=>q<="10000000"; 
when "1001"=>q<="10010000"; 
when others=>q<="11111111"; 
end case; 
end process; 
end disp_arc;