cnt90.vhd

来自「多功能数字钟的设计」· VHDL 代码 · 共 45 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt90 IS
 PORT(clk,clr: IN STD_LOGIC;
      ten,one: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      co: OUT STD_LOGIC);
END cnt90;
ARCHITECTURE are OF cnt90 is
   signal cin:std_logic;
begin
 PROCESS(clk,clr)
  VARIABLE cnt0: STD_LOGIC_VECTOR(3 DOWNTO 0);
 BEGIN
  IF clr='1' THEN
     cnt0:="0000";
  ELSIF clk 'EVENT AND clk='1' THEN
     IF cnt0="1000" THEN
        cnt0:=cnt0+1;cin<='1';
     ELSIF cnt0="1001" THEN
         cin<='0'; cnt0:="0000";
     ELSE cnt0:=cnt0+1; cin<='0';
    end IF;
   END IF;
   one<=cnt0;
  END PROCESS;
  PROCESS(clk,clr,cin)
    VARIABLE cnt1: STD_LOGIC_VECTOR(3 DOWNTO 0);
  BEGIN
    IF clr='1' THEN
       cnt1:="0000";
       ELSIF clk 'EVENT AND clk='1' THEN
        IF cin='1' THEN
         IF  cnt1="1001" THEN
             cnt1:="0000";co<='1';
         ELSE cnt1:=cnt1+1;co<='0';
         END IF;
        END IF;
       ELSE cnt1:=cnt1;
      END IF;
      ten<=cnt1;
    END ProCESS;
END are;