mux24.vhd

多功能数字钟的设计

library ieee;
use ieee.std_logic_1164.all;
entity mux24 is
    port(sel:in std_logic_vector(2 downto 0);
         tenh,oneh: in std_logic_vector(3 downto 0);
         tenm,onem:in std_logic_vector(3 downto 0);
         tens,ones:in std_logic_vector(3 downto 0);
         q:out std_logic_vector(3 downto 0));
end;
architecture hav of mux24 is
begin
      process(sel)
    begin
        case sel is
          when "000"=>q<=ones;
          when "001"=>q<=tens;
          when "011"=>q<=onem;
          when "100"=>q<=tenm;
          when "101"=>q<=oneh;
          when "111"=>q<=tenh;
          when others=>q<="1111";
         end case;
   end process;
end hav;