cnt24.vhd

多功能数字钟的设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt24 is
   port(clk,clr:in std_logic;
        ten,one:out std_logic_vector(3 downto 0);
             co:out std_logic);
end;
architecture are of cnt24 is
  signal t10:std_logic_vector(3 downto 0);
  signal o1:std_logic_vector(3 downto 0);
  signal cin:std_logic;
begin
           ten<=t10;
           one<=o1;
 p1:process(clk,clr)
begin
 if clr='1' then
      o1<="0000";
 elsif clk'event and clk='1' then
   if(o1="1001")or(t10="0010"and o1="0011") then
          o1<="0000";cin<='0';
   elsif o1="1000" then
          o1<=o1+1;cin<='1';
   else o1<=o1+1;cin<='0';
   end if;
  end if;
end process p1;
p2:process(cin,clk,clr)
begin
  if clr='1' then
     t10<="0000";
  elsif clk'event and clk='1' then
        if(t10="0010" and o1="0011") then
           t10<="0000";co<='1';
        else co<='0';
        end if;
        if cin='1' then 
           t10<=t10+1;
         end if;
  end if;
end process p2;
end are;