array_mult_timesim.v

64位乘法器源码verilog,经过验证测试

// Xilinx Verilog netlist produced by netgen application (version G.31a)
// Command      : -intstyle ise -s 6 -pcf array_mult.pcf -ngm array_mult.ngm -w -ofmt verilog -sim array_mult.ncd array_mult_timesim.v 
// Input file   : array_mult.ncd
// Output file  : array_mult_timesim.v
// Design name  : array_mult
// # of Modules : 1
// Xilinx       : C:/Xilinx
// Device       : 2s50tq144-6 (PRODUCTION 1.27 2003-12-13)

// This verilog netlist is a simulation model and uses simulation 
// primitives which may not represent the true implementation of the 
// device, however the netlist is functionally correct and should not 
// be modified. This file cannot be synthesized and should only be used 
// with supported simulation tools.

`timescale 1 ns/1 ps

module array_mult (
p, y, x
);
  output [15 : 0] p;
  input [7 : 0] y;
  input [7 : 0] x;
  wire y_5_IBUF;
  wire x_3_IBUF;
  wire y_6_IBUF;
  wire y_4_IBUF;
  wire y_3_IBUF;
  wire y_2_IBUF;
  wire y_1_IBUF;
  wire x_4_IBUF;
  wire y_0_IBUF;
  wire p_10_OBUF;
  wire p_11_OBUF;
  wire p_12_OBUF;
  wire p_13_OBUF;
  wire p_14_OBUF;
  wire p_15_OBUF;
  wire x_0_IBUF;
  wire x_1_IBUF;
  wire x_2_IBUF;
  wire x_5_IBUF;
  wire x_6_IBUF;
  wire x_7_IBUF;
  wire y_7_IBUF;
  wire p_0_OBUF;
  wire p_1_OBUF;
  wire p_2_OBUF;
  wire p_3_OBUF;
  wire p_4_OBUF;
  wire p_5_OBUF;
  wire p_6_OBUF;
  wire p_7_OBUF;
  wire p_8_OBUF;
  wire p_9_OBUF;
  wire p5__n0015;
  wire p4__n0015;
  wire p3__n0015;
  wire p1__n0015;
  wire p7__n0015;
  wire \l_carry[4] ;
  wire N5386;
  wire \l_carry[2] ;
  wire p2__n0015;
  wire N5381;
  wire N5391;
  wire N7033;
  wire N7039;
  wire GSR = glbl.GSR;
  wire GTS = glbl.GTS;
  wire \c5<3>/FROM ;
  wire \c5<3>/GROM ;
  wire \c4<3>/FROM ;
  wire \c4<3>/GROM ;
  wire \c3<3>/FROM ;
  wire \c3<3>/GROM ;
  wire \c2<3>/FROM ;
  wire \c2<3>/GROM ;
  wire \c1<3>/FROM ;
  wire \c1<3>/GROM ;
  wire \p<10>/ENABLE ;
  wire \p<10>/TORGTS ;
  wire \p<10>/OUTMUX ;
  wire \p<11>/ENABLE ;
  wire \p<11>/TORGTS ;
  wire \p<11>/OUTMUX ;
  wire \p<12>/ENABLE ;
  wire \p<12>/TORGTS ;
  wire \p<12>/OUTMUX ;
  wire \p<13>/ENABLE ;
  wire \p<13>/TORGTS ;
  wire \p<13>/OUTMUX ;
  wire \p<14>/ENABLE ;
  wire \p<14>/TORGTS ;
  wire \p<14>/OUTMUX ;
  wire \p<15>/ENABLE ;
  wire \p<15>/TORGTS ;
  wire \p<15>/OUTMUX ;
  wire \x<0>/IBUF ;
  wire \x<1>/IBUF ;
  wire \x<2>/IBUF ;
  wire \x<3>/IBUF ;
  wire \y<0>/IBUF ;
  wire \x<4>/IBUF ;
  wire \y<1>/IBUF ;
  wire \x<5>/IBUF ;
  wire \y<2>/IBUF ;
  wire \x<6>/IBUF ;
  wire \y<3>/IBUF ;
  wire \x<7>/IBUF ;
  wire \y<4>/IBUF ;
  wire \y<5>/IBUF ;
  wire \y<6>/IBUF ;
  wire \y<7>/IBUF ;
  wire \p<0>/ENABLE ;
  wire \p<0>/TORGTS ;
  wire \p<0>/OUTMUX ;
  wire \p<1>/ENABLE ;
  wire \p<1>/TORGTS ;
  wire \p<1>/OUTMUX ;
  wire \p<2>/ENABLE ;
  wire \p<2>/TORGTS ;
  wire \p<2>/OUTMUX ;
  wire \p<3>/ENABLE ;
  wire \p<3>/TORGTS ;
  wire \p<3>/OUTMUX ;
  wire \p<4>/ENABLE ;
  wire \p<4>/TORGTS ;
  wire \p<4>/OUTMUX ;
  wire \p<5>/ENABLE ;
  wire \p<5>/TORGTS ;
  wire \p<5>/OUTMUX ;
  wire \p<6>/ENABLE ;
  wire \p<6>/TORGTS ;
  wire \p<6>/OUTMUX ;
  wire \p<7>/ENABLE ;
  wire \p<7>/TORGTS ;
  wire \p<7>/OUTMUX ;
  wire \p<8>/ENABLE ;
  wire \p<8>/TORGTS ;
  wire \p<8>/OUTMUX ;
  wire \p<9>/ENABLE ;
  wire \p<9>/TORGTS ;
  wire \p<9>/OUTMUX ;
  wire \c6<1>/FROM ;
  wire \c6<1>/GROM ;
  wire \p5__n0015/FROM ;
  wire \p5__n0015/GROM ;
  wire \p4__n0015/FROM ;
  wire \p4__n0015/GROM ;
  wire \p3__n0015/FROM ;
  wire \p3__n0015/GROM ;
  wire \p_1_OBUF/FROM ;
  wire \p_1_OBUF/GROM ;
  wire \row1<5>/FROM ;
  wire \row1<5>/GROM ;
  wire \row1<6>/FROM ;
  wire \row1<6>/GROM ;
  wire \row7<6>/FROM ;
  wire \row7<6>/GROM ;
  wire \N5386/FROM ;
  wire \N5386/GROM ;
  wire \p_10_OBUF/GROM ;
  wire \row1<3>/FROM ;
  wire \row1<3>/GROM ;
  wire \c6<6>/FROM ;
  wire \c6<6>/GROM ;
  wire \c5<6>/FROM ;
  wire \c5<6>/GROM ;
  wire \c4<6>/FROM ;
  wire \c4<6>/GROM ;
  wire \c3<6>/FROM ;
  wire \c3<6>/GROM ;
  wire \c2<6>/FROM ;
  wire \c2<6>/GROM ;
  wire \c1<6>/FROM ;
  wire \c1<6>/GROM ;
  wire \N5381/FROM ;
  wire \N5381/GROM ;
  wire \row6<2>/FROM ;
  wire \row6<2>/GROM ;
  wire \row1<2>/FROM ;
  wire \row1<2>/GROM ;
  wire \p_7_OBUF/FROM ;
  wire \p_7_OBUF/GROM ;
  wire \c6<4>/FROM ;
  wire \c6<4>/GROM ;
  wire \c5<4>/FROM ;
  wire \c5<4>/GROM ;
  wire \c4<4>/FROM ;
  wire \c4<4>/GROM ;
  wire \c3<4>/FROM ;
  wire \c3<4>/GROM ;
  wire \c2<4>/FROM ;
  wire \c2<4>/GROM ;
  wire \c1<4>/FROM ;
  wire \c1<4>/GROM ;
  wire \N5391/FROM ;
  wire \N5391/GROM ;
  wire \N7033/FROM ;
  wire \N7033/GROM ;
  wire \p7__n0015/FROM ;
  wire \p7__n0015/GROM ;
  wire \c5<2>/FROM ;
  wire \c5<2>/GROM ;
  wire \p_3_OBUF/FROM ;
  wire \p_3_OBUF/GROM ;
  wire \c7<5>/FROM ;
  wire \c7<5>/GROM ;
  wire \c6<2>/FROM ;
  wire \c6<2>/GROM ;
  wire \c4<2>/FROM ;
  wire \c4<2>/GROM ;
  wire \c3<2>/FROM ;
  wire \c3<2>/GROM ;
  wire \c2<2>/FROM ;
  wire \c2<2>/GROM ;
  wire \c1<2>/FROM ;
  wire \c1<2>/GROM ;
  wire \c1<0>/FROM ;
  wire \c1<0>/GROM ;
  wire \p_11_OBUF/GROM ;
  wire \p_8_OBUF/FROM ;
  wire \p_8_OBUF/GROM ;
  wire \N7039/FROM ;
  wire \N7039/GROM ;
  wire \p2__n0015/GROM ;
  wire \c6<5>/FROM ;
  wire \c6<5>/GROM ;
  wire \c5<5>/FROM ;
  wire \c5<5>/GROM ;
  wire \c4<5>/FROM ;
  wire \c4<5>/GROM ;
  wire \c3<5>/FROM ;
  wire \c3<5>/GROM ;
  wire \c2<5>/FROM ;
  wire \c2<5>/GROM ;
  wire \c1<5>/FROM ;
  wire \c1<5>/GROM ;
  wire \row6<1>/FROM ;
  wire \row6<1>/GROM ;
  wire \row5<1>/FROM ;
  wire \row5<1>/GROM ;
  wire \row4<1>/FROM ;
  wire \row4<1>/GROM ;
  wire \row3<1>/FROM ;
  wire \row3<1>/GROM ;
  wire \row2<1>/FROM ;
  wire \row2<1>/GROM ;
  wire \row1<1>/FROM ;
  wire \row1<1>/GROM ;
  wire \c7<3>/GROM ;
  wire \c6<3>/FROM ;
  wire \c6<3>/GROM ;
  wire VCC;
  wire [6 : 0] c4;
  wire [6 : 1] row4;
  wire [6 : 1] row5;
  wire [6 : 0] c5;
  wire [6 : 1] row6;
  wire [6 : 0] c3;
  wire [6 : 1] row3;
  wire [6 : 0] c2;
  wire [6 : 1] row2;
  wire [6 : 0] c1;
  wire [6 : 1] row1;
  wire [6 : 0] c6;
  wire [6 : 1] row7;
  wire [6 : 0] c7;
  initial $sdf_annotate("array_mult_timesim.sdf");
  defparam \p4_Madd__AUX_4_Mxor_Result<1>_Result1 .INIT = 16'hE888;
  X_LUT4 \p4_Madd__AUX_4_Mxor_Result<1>_Result1  (
    .ADR0(c4[3]),
    .ADR1(row4[4]),
    .ADR2(x_3_IBUF),
    .ADR3(y_5_IBUF),
    .O(\c5<3>/FROM )
  );
  defparam \p5_Madd__AUX_4_Mxor_Result<0>_Result1 .INIT = 16'h956A;
  X_LUT4 \p5_Madd__AUX_4_Mxor_Result<0>_Result1  (
    .ADR0(row5[4]),
    .ADR1(x_3_IBUF),
    .ADR2(y_6_IBUF),
    .ADR3(c5[3]),
    .O(\c5<3>/GROM )
  );
  X_BUF \c5<3>/XUSED  (
    .I(\c5<3>/FROM ),
    .O(c5[3])
  );
  X_BUF \c5<3>/YUSED  (
    .I(\c5<3>/GROM ),
    .O(row6[3])
  );
  defparam \p3_Madd__AUX_4_Mxor_Result<1>_Result1 .INIT = 16'hE8A0;
  X_LUT4 \p3_Madd__AUX_4_Mxor_Result<1>_Result1  (
    .ADR0(row3[4]),
    .ADR1(x_3_IBUF),
    .ADR2(c3[3]),
    .ADR3(y_4_IBUF),
    .O(\c4<3>/FROM )
  );
  defparam \p4_Madd__AUX_4_Mxor_Result<0>_Result1 .INIT = 16'h8778;
  X_LUT4 \p4_Madd__AUX_4_Mxor_Result<0>_Result1  (
    .ADR0(y_5_IBUF),
    .ADR1(x_3_IBUF),
    .ADR2(row4[4]),
    .ADR3(c4[3]),
    .O(\c4<3>/GROM )
  );
  X_BUF \c4<3>/XUSED  (
    .I(\c4<3>/FROM ),
    .O(c4[3])
  );
  X_BUF \c4<3>/YUSED  (
    .I(\c4<3>/GROM ),
    .O(row5[3])
  );
  defparam \p2_Madd__AUX_4_Mxor_Result<1>_Result1 .INIT = 16'hE8A0;
  X_LUT4 \p2_Madd__AUX_4_Mxor_Result<1>_Result1  (
    .ADR0(c2[3]),
    .ADR1(x_3_IBUF),
    .ADR2(row2[4]),
    .ADR3(y_3_IBUF),
    .O(\c3<3>/FROM )
  );
  defparam \p3_Madd__AUX_4_Mxor_Result<0>_Result1 .INIT = 16'h936C;
  X_LUT4 \p3_Madd__AUX_4_Mxor_Result<0>_Result1  (
    .ADR0(y_4_IBUF),
    .ADR1(row3[4]),
    .ADR2(x_3_IBUF),
    .ADR3(c3[3]),
    .O(\c3<3>/GROM )
  );
  X_BUF \c3<3>/XUSED  (
    .I(\c3<3>/FROM ),
    .O(c3[3])
  );
  X_BUF \c3<3>/YUSED  (
    .I(\c3<3>/GROM ),
    .O(row4[3])
  );
  defparam \p1_Madd__AUX_4_Mxor_Result<1>_Result1 .INIT = 16'hEC80;
  X_LUT4 \p1_Madd__AUX_4_Mxor_Result<1>_Result1  (
    .ADR0(y_2_IBUF),
    .ADR1(c1[3]),
    .ADR2(x_3_IBUF),
    .ADR3(row1[4]),
    .O(\c2<3>/FROM )
  );
  defparam \p2_Madd__AUX_4_Mxor_Result<0>_Result1 .INIT = 16'h8778;
  X_LUT4 \p2_Madd__AUX_4_Mxor_Result<0>_Result1  (
    .ADR0(x_3_IBUF),
    .ADR1(y_3_IBUF),
    .ADR2(row2[4]),
    .ADR3(c2[3]),
    .O(\c2<3>/GROM )
  );
  X_BUF \c2<3>/XUSED  (
    .I(\c2<3>/FROM ),
    .O(c2[3])
  );
  X_BUF \c2<3>/YUSED  (
    .I(\c2<3>/GROM ),
    .O(row3[3])
  );
  defparam \p0/Madd__AUX_4_Mxor_Result<1>_Result1 .INIT = 16'h8000;
  X_LUT4 \p0/Madd__AUX_4_Mxor_Result<1>_Result1  (
    .ADR0(x_4_IBUF),
    .ADR1(y_1_IBUF),
    .ADR2(x_3_IBUF),
    .ADR3(y_0_IBUF),
    .O(\c1<3>/FROM )
  );
  defparam \p1_Madd__AUX_4_Mxor_Result<0>_Result1 .INIT = 16'h8778;
  X_LUT4 \p1_Madd__AUX_4_Mxor_Result<0>_Result1  (
    .ADR0(y_2_IBUF),
    .ADR1(x_3_IBUF),
    .ADR2(row1[4]),
    .ADR3(c1[3]),
    .O(\c1<3>/GROM )
  );
  X_BUF \c1<3>/XUSED  (
    .I(\c1<3>/FROM ),
    .O(c1[3])
  );
  X_BUF \c1<3>/YUSED  (
    .I(\c1<3>/GROM ),
    .O(row2[3])
  );
  X_OPAD \p<10>/PAD  (
    .PAD(p[10])
  );
  X_TRI p_10_OBUF_0 (
    .I(\p<10>/OUTMUX ),
    .CTL(\p<10>/ENABLE ),
    .O(p[10])
  );
  X_INV \p<10>/ENABLEINV  (
    .I(\p<10>/TORGTS ),
    .O(\p<10>/ENABLE )
  );
  X_BUF \p<10>/GTS_OR  (
    .I(GTS),
    .O(\p<10>/TORGTS )
  );
  X_BUF \p<10>/OUTMUX_1  (
    .I(p_10_OBUF),
    .O(\p<10>/OUTMUX )
  );
  X_OPAD \p<11>/PAD  (
    .PAD(p[11])
  );
  X_TRI p_11_OBUF_2 (
    .I(\p<11>/OUTMUX ),
    .CTL(\p<11>/ENABLE ),
    .O(p[11])
  );
  X_INV \p<11>/ENABLEINV  (
    .I(\p<11>/TORGTS ),
    .O(\p<11>/ENABLE )
  );
  X_BUF \p<11>/GTS_OR  (
    .I(GTS),
    .O(\p<11>/TORGTS )
  );
  X_BUF \p<11>/OUTMUX_3  (
    .I(p_11_OBUF),
    .O(\p<11>/OUTMUX )
  );
  X_OPAD \p<12>/PAD  (
    .PAD(p[12])
  );
  X_TRI p_12_OBUF_4 (
    .I(\p<12>/OUTMUX ),
    .CTL(\p<12>/ENABLE ),
    .O(p[12])
  );
  X_INV \p<12>/ENABLEINV  (
    .I(\p<12>/TORGTS ),
    .O(\p<12>/ENABLE )
  );
  X_BUF \p<12>/GTS_OR  (
    .I(GTS),
    .O(\p<12>/TORGTS )
  );
  X_BUF \p<12>/OUTMUX_5  (
    .I(p_12_OBUF),
    .O(\p<12>/OUTMUX )
  );
  X_OPAD \p<13>/PAD  (
    .PAD(p[13])
  );
  X_TRI p_13_OBUF_6 (
    .I(\p<13>/OUTMUX ),
    .CTL(\p<13>/ENABLE ),
    .O(p[13])
  );
  X_INV \p<13>/ENABLEINV  (
    .I(\p<13>/TORGTS ),
    .O(\p<13>/ENABLE )
  );
  X_BUF \p<13>/GTS_OR  (
    .I(GTS),
    .O(\p<13>/TORGTS )
  );
  X_BUF \p<13>/OUTMUX_7  (
    .I(p_13_OBUF),
    .O(\p<13>/OUTMUX )
  );
  X_OPAD \p<14>/PAD  (
    .PAD(p[14])
  );
  X_TRI p_14_OBUF_8 (
    .I(\p<14>/OUTMUX ),
    .CTL(\p<14>/ENABLE ),
    .O(p[14])
  );
  X_INV \p<14>/ENABLEINV  (
    .I(\p<14>/TORGTS ),
    .O(\p<14>/ENABLE )
  );
  X_BUF \p<14>/GTS_OR  (
    .I(GTS),
    .O(\p<14>/TORGTS )
  );
  X_BUF \p<14>/OUTMUX_9  (
    .I(p_14_OBUF),
    .O(\p<14>/OUTMUX )
  );
  X_OPAD \p<15>/PAD  (
    .PAD(p[15])
  );
  X_TRI p_15_OBUF_10 (
    .I(\p<15>/OUTMUX ),
    .CTL(\p<15>/ENABLE ),
    .O(p[15])
  );
  X_INV \p<15>/ENABLEINV  (
    .I(\p<15>/TORGTS ),
    .O(\p<15>/ENABLE )
  );
  X_BUF \p<15>/GTS_OR  (
    .I(GTS),
    .O(\p<15>/TORGTS )
  );
  X_BUF \p<15>/OUTMUX_11  (
    .I(p_15_OBUF),
    .O(\p<15>/OUTMUX )
  );
  X_IPAD \x<0>/PAD  (
    .PAD(x[0])
  );
  X_BUF \x<0>/IMUX  (
    .I(\x<0>/IBUF ),
    .O(x_0_IBUF)
  );
  X_BUF x_0_IBUF_12 (
    .I(x[0]),
    .O(\x<0>/IBUF )
  );
  X_IPAD \x<1>/PAD  (
    .PAD(x[1])
  );
  X_BUF \x<1>/IMUX  (
    .I(\x<1>/IBUF ),
    .O(x_1_IBUF)
  );
  X_BUF x_1_IBUF_13 (
    .I(x[1]),
    .O(\x<1>/IBUF )
  );
  X_IPAD \x<2>/PAD  (
    .PAD(x[2])
  );
  X_BUF \x<2>/IMUX  (
    .I(\x<2>/IBUF ),
    .O(x_2_IBUF)
  );
  X_BUF x_2_IBUF_14 (
    .I(x[2]),
    .O(\x<2>/IBUF )
  );
  X_IPAD \x<3>/PAD  (
    .PAD(x[3])
  );
  X_BUF \x<3>/IMUX  (
    .I(\x<3>/IBUF ),
    .O(x_3_IBUF)
  );
  X_BUF x_3_IBUF_15 (
    .I(x[3]),
    .O(\x<3>/IBUF )