tb_edge.v

检测上升沿的verilog程序

module tb_edge;
reg clk,i_data_in,rst_n;
reg [4:0] cnt;
wire o_rising_edge;

edge_detection my_edge(clk,rst_n,i_data_in,o_rising_edge);

always # 5 clk=~clk;

initial
begin
            rst_n=1'b0;
    # 12    rst_n=1'b1;
            clk=1'b0;
            cnt=5'b0;
    # 2000  $finish;
end

always @(posedge clk)
    begin
        if(cnt==5'b11111)
            cnt<=5'b0;
        else
            cnt<=cnt+5'b1;
    end

always @(posedge clk)
    begin
        if(cnt==5'b00001||(cnt==5'b00101||cnt==5'b00110)||(cnt==5'b01111||cnt==5'b10000||cnt==5'b10001||cnt==5'b10010))
            i_data_in<=1'b1;
        //else if(cnt==0101||cnt==0110)
         //   i_data_in<=1;
        //else if(cnt==1101)
         //   i_data_in<=1;
        else 
            i_data_in<=1'b0;
    end

initial $shm_open ("waves.shm");
initial $shm_probe ("AS");    

initial $monitor($time,,,"o_rising_edge=%b cnt=%h ",o_rising_edge,cnt);

endmodule