clk_100div.vhd

应用VHDL语言将高稳晶振分频得到1pps

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-- Company: 
-- Engineer:
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-- Create Date:    16:24:57 09/09/07
-- Design Name:    
-- Module Name:    clk_100div - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_100div is
  port(clk:in std_logic;
         clk_div100:out std_logic);
end clk_100div;

architecture Behavioral of clk_100div is
	 component clk_10div 
    port(clk:in std_logic;
         clk_div10:out std_logic);
  end component clk_10div;
  signal clk_tmp:std_logic;
begin
	U1:clk_10div
	    port map(clk,clk_tmp);
	  U2:clk_10div
		 port map(clk_tmp,clk_div100);
end Behavioral;