clk_10div.vhd

应用VHDL语言将高稳晶振分频得到1pps

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-- Company: 
-- Engineer:
--
-- Create Date:    16:25:03 09/09/07
-- Design Name:    
-- Module Name:    clk_10div - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
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-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_10div is
	  port(clk:in std_logic;
         clk_div10:out std_logic);
end clk_10div;

architecture Behavioral of clk_10div is
   signal cnt:std_logic_vector(2 downto 0);
       signal clk_tmp:std_logic;
begin
  process(clk)
     constant md:std_logic_vector(2 downto 0):="100";     
     begin											 
          if(clk'event and clk='1')then
            if(cnt=md)then
	            cnt<=(others=>'0');
	            clk_tmp<=not clk_tmp;
	         else
	             cnt<=cnt+1;
	         end if;
	       end if;
     end process;
	  clk_div10<=clk_tmp;
end Behavioral;