clk_100div.syr

应用VHDL语言将高稳晶振分频得到1pps

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: clk_100div.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "clk_100div.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "clk_100div"
Output Format                      : NGC
Target Device                      : xc3s50-5-pq208

---- Source Options
Top Module Name                    : clk_100div
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : clk_100div.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/1PPS/clk_10div.vhd" in Library work.
Architecture behavioral of Entity clk_10div is up to date.
Compiling vhdl file "C:/1PPS/clk_100div.vhd" in Library work.
Architecture behavioral of Entity clk_100div is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <clk_100div> (Architecture <behavioral>).
Entity <clk_100div> analyzed. Unit <clk_100div> generated.

Analyzing Entity <clk_10div> (Architecture <behavioral>).
Entity <clk_10div> analyzed. Unit <clk_10div> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clk_10div>.
    Related source file is "C:/1PPS/clk_10div.vhd".
    Found 1-bit register for signal <clk_tmp>.
    Found 3-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <clk_10div> synthesized.


Synthesizing Unit <clk_100div>.
    Related source file is "C:/1PPS/clk_100div.vhd".
Unit <clk_100div> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 2
 3-bit up counter                  : 2
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clk_100div> ...

Optimizing unit <clk_10div> ...
Loading device for application Rf_Device from file '3s50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clk_100div, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : clk_100div.ngr
Top Level Output File Name         : clk_100div
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 2

Macro Statistics :
# Registers                        : 4
#      1-bit register              : 2
#      3-bit register              : 2

Cell Usage :
# BELS                             : 10
#      INV                         : 4
#      LUT2_L                      : 2
#      LUT3                        : 2
#      LUT3_L                      : 2
# FlipFlops/Latches                : 8
#      FDE                         : 2
#      FDR                         : 6
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 1
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s50pq208-5 

 Number of Slices:                       5  out of    768     0%  
 Number of Slice Flip Flops:             8  out of   1536     0%  
 Number of 4 input LUTs:                 6  out of   1536     0%  
 Number of bonded IOBs:                  2  out of    124     1%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
U1/clk_tmp:Q                       | NONE                   | 4     |
clk                                | BUFGP                  | 4     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 3.851ns (Maximum Frequency: 259.680MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 6.280ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'U1/clk_tmp:Q'
  Clock period: 3.851ns (frequency: 259.680MHz)
  Total number of paths / destination ports: 19 / 8
-------------------------------------------------------------------------
Delay:               3.851ns (Levels of Logic = 1)
  Source:            U2/cnt_0 (FF)
  Destination:       U2/cnt_2 (FF)
  Source Clock:      U1/clk_tmp:Q rising
  Destination Clock: U1/clk_tmp:Q rising

  Data Path: U2/cnt_0 to U2/cnt_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              4   0.626   1.074  U2/cnt_0 (U2/cnt_0)
     LUT3:I0->O            4   0.479   0.779  U2/_n00011 (U2/_n0001)
     FDR:R                     0.892          U2/cnt_0
    ----------------------------------------
    Total                      3.851ns (1.997ns logic, 1.854ns route)
                                       (51.9% logic, 48.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 3.851ns (frequency: 259.680MHz)
  Total number of paths / destination ports: 19 / 8
-------------------------------------------------------------------------
Delay:               3.851ns (Levels of Logic = 1)
  Source:            U1/cnt_0 (FF)
  Destination:       U1/cnt_2 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: U1/cnt_0 to U1/cnt_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              4   0.626   1.074  U1/cnt_0 (U1/cnt_0)
     LUT3:I0->O            4   0.479   0.779  U1/_n00011 (U1/_n0001)
     FDR:R                     0.892          U1/cnt_0
    ----------------------------------------
    Total                      3.851ns (1.997ns logic, 1.854ns route)
                                       (51.9% logic, 48.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'U1/clk_tmp:Q'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.280ns (Levels of Logic = 1)
  Source:            U2/clk_tmp (FF)
  Destination:       clk_div100 (PAD)
  Source Clock:      U1/clk_tmp:Q rising

  Data Path: U2/clk_tmp to clk_div100
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.626   0.745  U2/clk_tmp (U2/clk_tmp)
     OBUF:I->O                 4.909          clk_div100_OBUF (clk_div100)
    ----------------------------------------
    Total                      6.280ns (5.535ns logic, 0.745ns route)
                                       (88.1% logic, 11.9% route)

=========================================================================
CPU : 4.47 / 4.75 s | Elapsed : 4.00 / 4.00 s
 
--> 

Total memory usage is 97140 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)