qselect.vhd

VHDL语言实现时钟程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qselect is
port(qhh,qlh,qhm,qlm,qhs,qls:in std_logic_vector(3 downto 0);
		clk,clr:in std_logic;
        qout:out std_logic_vector(3 downto 0);
        qsel: out std_logic_vector(5 downto 0));
end entity qselect;
architecture beh of qselect is
signal sel:std_logic_vector(2 downto 0);
begin
process(clk,clr)
begin
if(clr='0')then
	sel<="000";
elsif(clk'event and clk='1')then
	if(sel=5)then
	sel<="000";
	else
	sel<=sel+1;
	end if;
end if;
end process;
process(clk,clr)
begin
if(clr='0')then
	qout<="0000";
	qsel<="111111";
	
elsif(clk'event and clk='1')then
    case sel is

		when "000"=>qout<=qhh;
	qsel<="011111";
		 when "001"=>qout<=qlh;
	qsel<="101111";

		 when "010"=>qout<=qhm;
	qsel<="110111";

		when "011"=>qout<=qlm;
	qsel<="111011";

		when "100"=>qout<=qhs;
	qsel<="111101";

		 when "101"=>qout<=qls;
	qsel<="111110";

	 when others  =>qout<="0000" ;
	qsel<="000000";
end case;
end if;
end process;
end beh;